Senior Staff Engineer, Digital IC Design

Job Title

Senior Staff Engineer, Digital IC Design

Role Summary

Work on SoC integration and digital IP design within the Custom Compute, Storage and Automotive Business Unit, delivering processor and subsystem blocks for high-performance compute, storage, networking, and automotive applications.

Lead portions of SoC designs through floorplanning, integration, verification, and tape-out while coordinating with architecture, verification, physical design, DFT, and packaging teams.

Experience Level

Senior — typically 5+ years professional experience; 3+ years with an advanced degree.

Responsibilities

Primary responsibilities include:

• Integrate internal and external IP blocks at the chip level and own interconnect and floorplan decisions.
• Own a portion of SoC design from initial stages to tape-out, including static checks and driving to timing closure.
• Assist and coordinate subsystem and chip-level verification and post-silicon debug.
• Lead RTL design efforts for internally developed processor IP and deliver micro-architectural specifications.
• Run functional and gate-level simulations, code quality checks, and CDC analyses using EDA tools.
• Develop and use automation and next-generation AI tools to accelerate development workflows.
• Collaborate cross-functionally with architecture, physical design, verification, DFT, and packaging teams to meet tape-out requirements.

Requirements

Must-have technical skills and experience:

• Proven experience in taping out complex SoCs and performing post-silicon debug.
• Strong RTL design skills in SystemVerilog.
• Hands-on SoC integration and debug experience, including clock/reset design, CDC, and timing constraints.
• Understanding of how front-end RTL decisions impact physical implementation and verification.
• Familiarity with ARM protocols (APB, AHB, AXI, CHI) and SoC interconnect / NOC architectures.
• Experience with scripting languages such as Python or Tcl.
• Strong communication, analytical, and problem-solving skills.

Nice-to-have:

• Experience leading processor IP design efforts and delivering micro-architectural specifications.
• Experience developing automation tools and applying AI tools to design workflows.

Education Requirements

Bachelor's degree in Computer Engineering, Electrical Engineering, or a related field plus 5+ years of relevant experience; OR Master's degree or PhD in those fields with 3+ years of relevant experience.

Expected Base Pay Range (USD): 134,390 - 201,300 per annum.

Reasonable accommodation: contact Marvell HR Helpdesk at TAOps@marvell.com.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.