Senior Staff Engineer, Digital IC Design

Job Title

Senior Staff Engineer, Digital IC Design

Role Summary

Senior ASIC design engineer responsible for post-RTL digital implementation and physical timing closure for SerDes and mixed-signal IP blocks. Works within the Central Engineering AMS‑IP team to deliver block- and chip-level synthesis, timing closure, DFT, and ECO support across Marvell product lines.

Experience Level

Senior — 6+ years of relevant ASIC/post-RTL design experience.

Responsibilities

Primary responsibilities focus on post-RTL design flow, physical implementation, and cross-team delivery of SerDes IPs.

• Lead block and/or chip-level synthesis, timing closure, DFT generation, and ECO implementation.
• Improve and maintain post-RTL design methodology and tool flows.
• Provide synthesis, timing, and DFT support for SerDes IPs (10Gbps–224Gbps) across product applications.
• Collaborate with analog and digital design teams to integrate and deliver IP solutions.
• Support product teams during pre-silicon and post-silicon stages, including debug and fixes.
• Perform custom placement and routing tasks for mixed-signal blocks as required.

Requirements

Must-have technical skills and competencies; a short list of desirable skills follows.

• Must-have: Post-RTL experience including synthesis, static timing analysis, and physical design; understanding of block and top-level timing closure.
• Logic or physical synthesis experience with Synopsys or Cadence tools.
• DFT generation and verification experience.
• Static timing analysis experience using PrimeTime.
• Physical design experience targeting 28nm and more advanced nodes.
• Strong Perl and Tcl scripting skills for automation.
• Ability to perform custom placement and routing for mixed-signal designs and to switch between post-RTL activities as needed.
• Good communication and teamwork skills; motivated and able to work in a high‑performance design team.

• Nice-to-have: Low-power design, circuit-level or custom design experience, floorplanning, clock-tree synthesis, power planning/analysis, signal integrity, and physical verification expertise.

Education Requirements

Master's degree and/or PhD in Electrical Engineering, Computer Science, or a related field. (The role expects candidates with 6+ years of relevant experience.)

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.