Senior Staff Engineer — Design Verification (VIP)
SynopsysJob Title
Senior Staff Engineer — Design Verification (VIP)
Role Summary
Responsible for designing, implementing, and maintaining Verification IP (VIP) and SystemVerilog/UVM-based verification environments for industry-standard protocols. Works with protocol experts, Design IP teams, and field teams to deliver reusable, scalable verification solutions used by semiconductor customers.
Primary focus is on coverage-driven verification, debugging complex protocol interactions, and supporting customer integration and deployment to ensure VIP quality and reliability.
Experience Level
Senior — typically requires 5+ years of hands-on experience in Verification IP or SystemVerilog/UVM-based testbench development (as specified in the posting).
Responsibilities
Core responsibilities include development, verification planning, and customer support for VIP products.
- Design, develop, and maintain Verification IP using SystemVerilog and UVM for protocols such as DFI, DRAM, AMBA, PCIe, USB, and Ethernet.
- Create comprehensive verification plans mapping protocol specifications to test scenarios, coverage goals, and corner-case strategies.
- Implement sequences, test scenarios, and checkers to drive functional and code-coverage verification.
- Debug complex simulation failures across multi-layer protocol stacks and customer integration environments.
- Enhance VIP for performance, reusability, and scalability as protocols and customer needs evolve.
- Support customers during VIP integration and deployment, troubleshooting issues and ensuring successful bring-up.
- Collaborate with Design IP teams, R&D engineers, and field teams to align VIP capabilities with product roadmaps.
Requirements
Must-have technical skills and experience; a short list of desirable additions is included.
- 5+ years of hands-on experience developing Verification IP or SystemVerilog/UVM-based testbenches.
- Deep working knowledge of at least two protocols (examples: AMBA AXI/AHB/APB, DFI, DRAM, PCIe, Ethernet).
- Strong proficiency in SystemVerilog and UVM methodology for building reusable, scalable verification environments.
- Proven ability to create and execute coverage-driven verification plans, including functional and code coverage analysis.
- Experience debugging complex simulation failures and resolving issues across protocol layers and integration boundaries.
- Excellent organization and ownership to manage multiple VIP enhancements, customer issues, and verification plans concurrently.
- Nice-to-have: prior experience working directly with customers or field teams during product deployment.
Education Requirements
Bachelor's or Master's degree in Electronics Engineering, Computer Science, or a closely related technical field — or equivalent practical experience.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
