Senior Staff Engineer, Design Verification (Verification IP)

Job Title

Senior Staff Engineer, Design Verification (Verification IP)

Role Summary

Design, develop, and maintain Verification IP (VIP) for industry protocols and lead coverage-driven verification efforts. Collaborate with R&D, design IP teams, and customer-facing teams to deliver scalable, reusable VIP and resolve complex integration and protocol issues.

Experience Level

Senior; requires 5+ years of relevant experience in Verification IP or SystemVerilog/UVM-based verification.

Responsibilities

Primary responsibilities include VIP development, verification planning, debugging, and customer support.

• Design, develop, and maintain VIP using SystemVerilog and UVM for protocols such as DFI, DRAM, AMBA, PCIe, USB, and Ethernet.
• Build verification plans that map protocol specifications to test scenarios, coverage goals, and corner-case strategies.
• Implement sequences, test scenarios, and checkers to drive coverage-based verification (functional and code coverage).
• Debug complex simulation failures across multi-layer protocol stacks; identify root causes in VIP logic and customer integration environments.
• Enhance VIP for performance, reusability, and scalability as protocols and customer use cases evolve.
• Support customers during VIP integration and deployment, troubleshoot issues, and answer technical questions.
• Collaborate with Design IP teams, R&D engineers, and field teams to align VIP capabilities with product roadmaps.

Requirements

Must-have technical skills and relevant hands-on experience; a few desirable additions listed below.

• Must-have: 5+ years hands-on experience developing Verification IP or SystemVerilog/UVM-based testbenches.
• Must-have: Strong proficiency in SystemVerilog and UVM methodology for building reusable, scalable verification environments.
• Must-have: Deep working knowledge of at least two industry-standard protocols (for example: AMBA/AXI/AHB/APB, DFI, DRAM, PCIe, Ethernet).
• Must-have: Experience creating and executing coverage-driven verification plans (functional and code coverage analysis).
• Must-have: Demonstrated ability to debug complex simulation failures and resolve integration issues across protocol layers.
• Nice-to-have: Experience working directly with customers or field teams during product deployment.

Education Requirements

Bachelor's or Master's degree in Electronics Engineering, Computer Science, or equivalent practical experience.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.