Senior Staff Engineer, Design Verification (Power & Analog ICs)
RenesasJob Title
Senior Staff Engineer, Design Verification (Power & Analog ICs)
Role Summary
Lead verification of digital content embedded in power, analog, and mixed-signal ICs as a senior individual contributor. Own verification architecture, methodology, execution, and sign-off at block and full-chip level.
Collaborate with analog, digital, architecture, applications, and test teams to ensure designs meet functional and product requirements before tape-out; mentor engineers and establish verification flows where required.
Experience Level
Senior-level. Requires 10+ years of experience in digital verification and leadership of verification efforts.
Responsibilities
Primary responsibilities include planning, implementing, and delivering verification for complex mixed-signal products.
- Define and own block-level and full-chip verification strategy, plans, coverage goals, and sign-off criteria.
- Build reusable, scalable verification environments and decomposed verification components from specifications.
- Design and develop SystemVerilog/UVM testbenches, agents, scoreboards, assertions, sequences, and coverage models.
- Establish and run regression flows; perform triage, debug, and coverage closure to achieve sign-off.
- Apply simulation, assertion-based verification, formal methods, and FPGA/emulation where appropriate.
- Verify digital behavior across reset, clock, power-state, fault, trim, communication, test-mode, and analog-interaction scenarios.
- Collaborate with cross-functional teams to close specification gaps and verify analog-digital interactions at appropriate abstraction levels.
- Support DFT, scan/ATPG, gate-level/timing-aware and post-layout verification; contribute to silicon bring-up and root-cause analysis.
- Drive verification methodology, automation, metrics, documentation; mentor engineers and report status/coverage/risk to leadership.
Requirements
Core technical and professional requirements.
- Must-have: 10+ years of hands-on digital verification experience with SystemVerilog and UVM; proven ownership of block and full-chip verification and sign-off for complex semiconductor products.
- Strong knowledge of functional verification, assertion-based verification, formal verification, regression frameworks, coverage closure, and debug methodologies.
- Experience verifying digital logic embedded in PMICs, power-management, automotive, audio, or other mixed-signal ICs; good understanding of RTL, microarchitecture, clocks, resets, low-power states, register interfaces, and serial interfaces (SPI, I2C, UART).
- Working knowledge of synthesis, STA, DFT, scan insertion, ATPG, and gate-level verification; experience with scripting/automation (Python, TCL, Perl, shell).
- Proven ability to mentor engineers, establish verification methodology, lead technical reviews, and deliver under tight, multisite schedules.
- Nice-to-have: Practical experience with FPGA/emulation flows, formal tool application in mixed-signal contexts, and production-test vector development.
Education Requirements
Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, or a related discipline.
About the Company
Company: Renesas
Headquarters: Hitachinaka, Japan
Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.
