Senior/Staff Engineer, Design Verification

Job Title

Senior/Staff Engineer, Design Verification

Role Summary

Lead and execute IP- and subsystem-level functional verification for SoC projects, owning verification strategy, environment development, and closure metrics from specification to sign-off.

Work closely with RTL architects, SoC verification, emulation, and post-silicon teams to ensure robust verification, reusability, and timely delivery of IP for SoC integration.

Experience Level

Senior level. The posting lists 2–8 years of SoC verification experience as guidance.

Responsibilities

Primary responsibilities include delivering verification solutions and driving coverage- and metric-based sign-off:

• Plan and execute end-to-end verification for complex digital IPs and subsystems.
• Define IP-level verification strategies, test plans, coverage models, and closure criteria.
• Design and develop scalable, reusable UVM-based verification environments.
• Drive functional, code, assertion, and cross-coverage closure with clear metrics.
• Apply AI/ML-assisted techniques to accelerate coverage convergence and optimize regressions.
• Develop advanced checkers, scoreboards, SVA assertions, and protocol monitors.
• Use constraint-random and directed tests for protocol, corner-case, and stress verification.
• Collaborate with RTL, architecture, emulation, and SoC teams for integration and issue resolution.
• Mentor junior engineers and promote verification best practices; support GLS, low-power verification, and post-silicon debug as needed.

Requirements

Must-have technical skills and experience:

• Strong expertise in UVM-based testbench architecture and development.
• Deep understanding of SystemVerilog, assertions (SVA), and verification best practices.
• Proven experience in metric-driven verification, including functional and code coverage closure.
• Experience with directed and constrained-random verification methodologies.
• Experience debugging complex issues in simulation, emulation, and post-silicon environments.
• Proficiency in Verilog/SystemVerilog; working knowledge of C/C++ and shell scripting.
• Familiarity with industry-standard EDA toolkits and verification flows.
• Strong analytical, problem-solving, and communication skills; demonstrated ability to mentor others.

Nice-to-have:

• Hands-on experience with AI/ML-based verification tools for coverage analysis and regression optimization.
• Scripting expertise in Python, Perl, or TCL for automation and analytics.
• Exposure to formal verification or hybrid formal-simulation flows.
• Familiarity with high-speed codecs or safety/security-critical IPs (e.g., H.264, security/debug domains).

Education Requirements

Bachelor's or master's degree in Electronics Engineering.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.