Senior Staff Engineer, Design Verification
Marvell TechnologyJob Title
Senior Staff Engineer, Design Verification
Role Summary
Join the Infrastructure Processor Business Unit to verify complex CPU subsystems and full SoC designs for high-performance, low-power processor products. The role focuses on hands-on verification work, testbench architecture, and delivering verification closure for IP and subsystems.
The position includes technical leadership responsibilities: developing verification flows and methodologies, mentoring verification engineers, and coordinating with design and software teams to meet customer and product requirements.
Experience Level
Senior — the posting indicates a typical range of experience: Bachelor's degree holders with ~8–12 years' relevant experience, or candidates with a Master's/PhD and ~6+ years' experience.
Responsibilities
Primary responsibilities include planning and executing verification for processor IP, subsystems, and SoC-level integration.
- Plan and execute design verification for complex CPU subsystems and full SoC.
- Architect, implement, and maintain SystemVerilog/UVM testbenches and verification environments.
- Develop test plans, coverage plans, directed and constrained-random tests, and achieve verification closure.
- Mentor and guide a team of design verification engineers and lead verification reviews.
- Debug failing tests and silicon issues using industry tools and methodologies; own debug and root-cause processes.
- Own verification flows, methodologies, and IP/subsystem verification to meet defined criteria.
- Collaborate with design, architecture, software, and validation teams to ensure protocol and system correctness.
Requirements
Key technical skills and qualifications for the role.
- Proven hands-on experience with SystemVerilog and UVM for environment and test development.
- SoC-level digital design verification and ASIC verification experience, including environment development through test generation.
- Experience with constrained-random stimulus and functional coverage methodologies.
- Strong debug skills and experience with debug tools such as Verdi and Incisive.
- Good knowledge of AMBA protocols (AXI, AHB, APB) and general SoC interfaces.
- Experience creating test benches, test plans, and coverage plans from scratch on at least one complex project.
- Familiarity with GIT version control and basic exposure to the C programming language.
- Ability to lead verification flows and mentor engineers; strong communication and collaboration skills.
- Must be eligible to access export-controlled technology where applicable.
Education Requirements
Posting specifies a Bachelor's degree in Computer Science, Electrical Engineering, or related fields (with ~8–12 years' experience) or a Master’s/PhD in Computer Science, Electrical Engineering, or related fields (with ~6+ years' experience). No certifications or equivalent-experience clauses were listed.
About the Company
Company: Marvell Technology
Headquarters: Santa Clara, California, United States
Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.
