Senior Staff Engineer, Custom IC Layout

Job Title

Senior Staff Engineer, Custom IC Layout

Role Summary

Customer-facing senior engineer responsible for enabling Synopsys Custom Compiler and layout-synthesis adoption at leading Korean foundry, memory, and fabless customers. The role leads on-site debug, develops migration methodologies, validates advanced-node flows, and partners with R&D and field teams to prioritize product improvements.

Experience Level

Senior-level - requires 7+ years of hands-on experience in custom IC layout or equivalent EDA product/application engineering supporting custom layout tools.

Responsibilities

Core responsibilities focus on deploying tools and methodologies, resolving tapeout-blocking issues, and scaling migration and synthesis flows for customers.

• Lead technical engagement and tool deployment for Custom Compiler at major Korean customers.
• Perform on-site debug and root-cause analysis; deliver patches, workarounds, and hotfixes aligned to tapeout schedules.
• Develop and validate node-to-node and fab-to-fab analog IP migration methodologies and production-ready flows.
• Drive adoption and integration of layout synthesis (ASO.ai and Synopsys.ai) into customer workflows and demonstrate ROI on real designs.
• Create and deliver methodology decks, application notes, training materials, and workshops for layout engineers.
• Validate new Custom Compiler features on customer reference designs and provide actionable feedback to R&D.
• Collaborate with field application teams and R&D to influence product roadmap based on customer requirements.

Requirements

Must-have technical skills and background to perform the role.

• 7+ years experience in custom IC layout for analog, mixed-signal, memory, standard cell, or IP blocks, or in EDA product/application engineering supporting custom layout tools.
• Proficiency with Synopsys Custom Compiler or Cadence Virtuoso, including layout editors, DRC/LVS flows, and parasitic extraction.
• Strong knowledge of advanced-node design rules, physical verification flows, and parasitic-aware layout techniques.
• Scripting experience in SKILL, Python, or Tcl and comfort with Linux/Unix environments for automation and debugging.
• Fluency in Korean and strong English communication skills; experience presenting technical content to executives and engineering teams.
• Comfort with frequent travel to customer sites in Korea to support on-site engagements.

Nice-to-have:

• Hands-on experience with analog IP migration across process nodes or foundries.
• Practical experience with layout synthesis tools and demonstrating productivity gains on production designs.

Education Requirements

BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related technical field.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.