Senior Staff Engineer, Custom IC Layout

Job Title

Senior Staff Engineer, Custom IC Layout

Role Summary

Work on Custom Compiler product engineering to enable custom IC layout for leading Korean foundry, memory, and fabless customers. The role focuses on customer-facing debugging, methodology development, migration flows, and collaboration with R&D and Synopsys.ai to deliver production-ready layouts at advanced process nodes.

Position is part of the Custom Compiler Product Engineering team and requires regular on-site engagement in Korea to resolve tapeout-critical issues and drive tool adoption.

Experience Level

Senior-level. Requires 7+ years of hands-on experience in custom IC layout, EDA product engineering, or application engineering supporting custom layout tools.

Responsibilities

Primary responsibilities include technical customer engagement, root-cause debugging, methodology development, and enabling layout synthesis.

• Lead technical engagement and tool deployment for Custom Compiler at Korean foundry, memory, and fabless customers.
• Perform on-site debug and root-cause analysis; deliver patches, workarounds, and hotfixes aligned to customer tapeout schedules.
• Develop and validate node-to-node and fab-to-fab analog IP migration methodologies and scalable flows.
• Drive adoption and integration of layout synthesis (ASO.ai and Synopsys.ai) into customer workflows and demonstrate ROI on real designs.
• Create methodology decks, application notes, training materials, and run customer workshops for layout engineers.
• Validate new Custom Compiler features on customer reference designs and provide actionable feedback to R&D before general release.
• Collaborate with field application teams and R&D to define product roadmap priorities based on direct customer engagement.

Requirements

Must-have technical skills and experience; a few strong differentiators listed as nice-to-have.

• Must-have: 7+ years hands-on experience in custom IC layout (analog, mixed-signal, memory, standard-cell, or IP) or in EDA product/application engineering supporting custom layout tools.
• Must-have: Proficiency with Synopsys Custom Compiler or Cadence Virtuoso, including layout editors, DRC/LVS flows, and parasitic extraction.
• Must-have: Strong knowledge of advanced-node design rules, physical verification flows, and parasitic-aware layout techniques.
• Must-have: Scripting experience in SKILL, Python, or Tcl and comfort working in Linux/Unix for automation and debugging.
• Must-have: Fluency in Korean and strong English communication skills; ability to present technical content to executives and lead engineering workshops.
• Nice-to-have: Practical experience with analog IP migration across process nodes or foundries.
• Nice-to-have: Hands-on experience deploying layout synthesis tools on production designs.

Education Requirements

BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related technical field.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.