Senior Staff Engineer, ASIC/VLSI Synthesis and Design

Job Title

Senior Staff Engineer, ASIC/VLSI Synthesis and Design

Role Summary

Lead synthesis and front-end ASIC implementation activities for high-speed SoC and block designs, focused on timing constraint development, logic synthesis, and timing closure for advanced-node designs.

Work on Photonic Fabric and related high-bandwidth interconnect projects, collaborating with architecture, RTL, DFT, analog, and physical design teams to deliver production-ready netlists.

Experience Level

Senior-level role. Candidate should have substantial industry experience; typical hires meet or exceed five years of ASIC implementation and synthesis experience.

Responsibilities

Primary responsibilities include front-end synthesis, timing, and delivery of netlists for complex SoC projects.

• Develop and validate timing constraints for complex hierarchical SoC designs.
• Collaborate with Architecture, RTL, DFT, and Analog teams to define consolidated timing modes and constraints for synthesis, PnR, and chip sign-off.
• Own front-end implementation flows: synthesis, UPF development, logical equivalence checks (LEC), and functional ECOs.
• Perform physical-aware synthesis and timing optimization using industry tools (e.g., Fusion Compiler).
• Analyze power/performance/area tradeoffs and incorporate them into implementation flows.
• Resolve EDA tool issues independently or with vendor support.
• Automate front-end flows and processes using scripting (Tcl, Python, etc.).
• Ensure compliance with netlist handoff checklists and criteria for delivery to physical design.
• Document best practices and lessons learned to improve future projects.

Requirements

Must-have technical skills and experience for immediate contribution.

• Minimum ~5 years industry experience in ASIC implementation and synthesis (see Education Requirements for degree-related experience guidance).
• Strong understanding of RTL-to-GDSII ASIC design flows and timing closure methodologies.
• Hands-on experience with synthesis and STA methodologies; familiarity with LEC and ECO flows (e.g., Conformal ECO).
• Experience with UPF development and UPF validation tools (e.g., Conformal Low Power).
• Experience with physical-aware synthesis and advanced-node designs (tool experience preferred).
• Proficiency in scripting for automation (Tcl, Python, Perl or similar).
• Ability to analyze and debug complex timing and implementation issues; strong problem-solving skills.
• Effective communication and collaboration within cross-functional teams.

Education Requirements

Bachelor's degree in Computer Science, Electrical Engineering, or a related field (with 5–10 years' relevant experience) OR a Master's degree or PhD in Computer Science, Electrical Engineering, or a related field (with ~3–5 years' relevant experience). No certifications specified. Equivalent professional experience is not explicitly stated.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.