Senior Staff Engineer, ASIC/VLSI Synthesis and Design

Job Title

Senior Staff Engineer, ASIC/VLSI Synthesis and Design

Role Summary

Senior engineering role responsible for synthesis and front-end implementation of complex SoC and block-level designs. Works with architecture, RTL, DFT, analog, and physical design teams to develop timing constraints, drive timing closure, and deliver production-ready netlists.

The team focuses on high-performance data-center interconnect and photonic fabric solutions; the role emphasizes timing, synthesis methodology, and automation for advanced nodes.

Experience Level

Senior level. The posting requests 5–10 years of related experience for candidates with a Bachelor's degree, or 3–5 years with a Master's/PhD.

Responsibilities

Primary responsibilities include defining synthesis/timing flows and ensuring timing closure for high-speed SoC designs.

• Develop and validate timing constraints for complex SoC and hierarchical block designs.
• Collaborate with Architecture, RTL, DFT, Analog, and PD teams to consolidate timing modes and constraints for synthesis, PnR, and sign-off.
• Own front-end implementation tasks: synthesis, UPF development, logical equivalence checks (LEC), and functional ECOs.
• Perform physical-aware synthesis and timing optimization using tools such as Fusion Compiler.
• Analyze power/performance/area trade-offs and translate them into implementation decisions.
• Resolve EDA tool issues directly or work with tool vendors to find workarounds.
• Automate front-end flows and processes using scripting (Tcl, Python, etc.).
• Ensure compliance with netlist handoff checklists and document best practices for future projects.

Requirements

Core technical qualifications and skills required. Education details are summarized separately below.

• Must-have: Minimum of 5 years of industry experience in ASIC implementation and synthesis.
• Must-have: Strong understanding of full ASIC design flows from RTL to GDSII, and of synthesis and STA methodologies.
• Must-have: Experience with logical equivalence checks, functional ECO flows, and UPF development and validation.
• Must-have: Proficiency in EDA synthesis and STA tools and in scripting for automation (Tcl, Python; Perl experience noted).
• Must-have: Experience delivering timing closure and meeting performance, power, and area targets on complex designs.
• Nice-to-have: Hands-on experience with physical-aware synthesis tools (e.g., Fusion Compiler) and low-power validation tools (e.g., Conformal Low Power).
• Nice-to-have: Experience with advanced process nodes; familiarity with TSMC N4/N5 preferred.
• Nice-to-have: Experience working with EDA vendors to diagnose and resolve tool issues.

Education Requirements

Required: Bachelor's degree in Computer Science, Electrical Engineering, or a related field (with 5–10 years' experience), or a Master's or PhD in Computer Science, Electrical Engineering, or related fields with 3–5 years' experience. Equivalent practical experience in ASIC implementation and synthesis may be acceptable where stated.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.