Senior Staff Engineer, ASIC Design/Implementation — LEC/STA/Power Analysis

Job Title

Senior Staff Engineer, ASIC Design/Implementation — LEC/STA/Power Analysis

Role Summary

Senior timing/STA engineer responsible for STA signoff, timing-constraint development, timing closure and QoR for complex SoC and block designs. Work within cross-functional teams (architecture, RTL, DFT, physical design, analog) to define signoff methodologies and drive deterministic timing closure.

Experience Level

Senior-level. Typical guidance: 5–10 years industry experience in ASIC timing/STA or 3–5 years with an advanced degree.

Responsibilities

Primary technical responsibilities focused on static timing analysis, signoff flows, and timing closure for advanced-node SoCs.

• Develop and validate timing constraints and consolidated timing modes for SoC and block-level signoff.
• Run STA signoff flows (post-route checks), define process corners, derates, and uncertainties.
• Create and manage timing ECOs, timing budgeting, and timing closure activities for high-speed designs.
• Automate STA flows and reporting using scripting (Tcl, Python) and produce QoR dashboards and histograms.
• Collaborate with Architecture, RTL, DFT and Physical teams to resolve timing issues and optimize designs.
• Investigate and resolve EDA tool issues; work with tool vendors when needed.
• Document signoff methodologies, best practices and lessons learned to improve future projects.

Requirements

Key must-have technical skills and experience. Education details are summarized separately below.

• Minimum of 5 years industry experience in ASIC timing and STA signoff for complex designs.
• Proven experience with STA tools and signoff flows (e.g., PrimeTime or equivalent).
• Strong skills in timing constraint development, hierarchical timing, and ECO creation.
• Proficiency in scripting to automate STA flows and generate reports (Tcl, Python; Perl is a plus).
• Familiarity with physical design and timing optimization techniques to achieve deterministic closure.
• Experience with advanced technology nodes (preferred: TSMC N4/N5 or similar deep nodes).
• Ability to analyze QoR, generate actionable reports/dashboards, and communicate findings to cross-functional teams.
• Problem-solving mindset with attention to detail and proven track record delivering designs on schedule.

Education Requirements

Bachelor's degree in Computer Science, Electrical Engineering or a related technical field is listed as typical, with alternatives: Master's or PhD in those fields. The posting allows equivalent professional experience in lieu of a degree. (Summary based on the job posting: B.S. + 5–10 years experience, or M.S./Ph.D. with 3–5 years.)

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.