Senior Staff Engineer, Analog Design

Job Title

Senior Staff Engineer, Analog Design

Role Summary

Lead architecture and analog/mixed-signal circuit design for Multi-Gbps SERDES IP targeting advanced FinFET and GAA process nodes. Drive sub-block design, collaborate with digital and layout teams, and support pre- and post-silicon validation for customer tape-outs and product releases.

Experience Level

Senior — typically MTech/MS with 8+ years or BTech/BS with 10+ years of hands-on analog IC design experience.

Responsibilities

Primary responsibilities include translating standards into architectures, designing sub-blocks, and supporting silicon bring-up.

• Review PCIe, Ethernet, USB, CXL and other SerDes standards and convert them into transceiver architectures and block-level specifications for NRZ and PAM4 designs.
• Architect and design analog/mixed-signal circuits: TX drivers, RX front-ends, adaptive equalizers, PLLs/DLLs, bandgaps, regulators, oscillators, and ADC/DAC blocks for advanced nodes.
• Collaborate with digital teams on co-design, calibration/adaptation algorithms, and timing handoff for seamless integration.
• Work with layout engineers to minimize parasitics, manage device stress and process variation, and ensure robust post-silicon performance.
• Present simulation results, design trade-offs, and architectural decisions in reviews and customer meetings.
• Document design methodologies, simulation approaches, test plans, and characterization; support post-silicon bring-up and debug.
• Analyze customer silicon and field data to drive design updates for next-generation IP.

Requirements

Key technical must-haves and desirable skills.

• Proven CMOS tape-outs in FinFET technologies with demonstrated Multi-Gbps NRZ and PAM4 design experience.
• Deep expertise in SERDES sub-circuits: TX drivers, RX front-ends, adaptive equalizers, PLLs/DLLs, regulators, oscillators, and data converters.
• Strong understanding of analog/digital co-design, calibration/adaptation algorithms, and timing handoff between analog and digital domains.
• Proficiency with schematic entry, physical-layout collaboration, design verification, and SPICE simulators (Spectre or HSPICE).
• Experience with scripting for simulation post-processing and automation (TCL, Perl, MATLAB).
• Solid system-level budgeting for jitter, amplitude, and noise; familiarity with packaging parasitics, crosstalk, and channel loss.
• Experience supporting post-silicon bring-up, debug, and field-data analysis to drive design improvements.
• Nice-to-have: experience with ESD protection, custom digital design, and design-for-reliability topics (electromigration, IR drop, aging, self-heating).

Education Requirements

MTech or MS with 8+ years of hands-on analog IC design experience, or BTech or BS with 10+ years, in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.