Senior/Staff Emulation Engineer

Job Title

Senior/Staff Emulation Engineer

Role Summary

Join the Emulation team in Hardware to build emulation infrastructure, flows, and debug methodology for high-performance connectivity SoCs. The role spans emulation, SoC simulation, firmware/software bring-up, and post-silicon validation and focuses on reusable, scalable flows across projects.

This is a hybrid role based at the Mountain View HQ working closely with architecture, RTL, DV, firmware, driver, kernel, validation, and EDA/vendor teams.

Experience Level

Senior-level (Senior/Staff). The posting targets experienced engineers; no explicit years-of-experience range was specified.

Responsibilities

Primary responsibilities include building and scaling emulation-based validation and debug infrastructure for complex connectivity SoCs.

• Define and execute emulation strategy and test plans for connectivity SoCs.
• Bring up and debug large models on commercial emulation platforms (e.g., Cadence Palladium, Zebu, Veloce).
• Integrate external adapters and memory models (PCIe, HBM4, Ethernet, AXI/AMBA, JTAG, QSPI) and develop custom transactors when needed.
• Develop HW/SW co-emulation and co-simulation flows using RTL, software/reference models (Rust, C/C++, SystemC), firmware, and software tests.
• Build reusable transactors, agents, stubs, bridges, checkers, and acceleration flows.
• Optimize emulation speed and resource use: partitioning, clocking, regression scheduling, multi-user capacity, and trace management.
• Automate regression triage, debug workflows, and engineering productivity tooling.
• Develop practical LLM-based tools for log analysis, waveform triage, debug assistance, and flow generation.
• Collaborate with cross-functional teams and vendors to ensure end-to-end validation and bring-up.

Requirements

Must-have technical skills and constraints for this role.

• Hands-on experience with SoC emulation or system-level validation and the ability to deliver emulation-driven validation projects.
• Experience with at least one commercial emulation platform (example: Cadence Palladium, Zebu, Veloce).
• Working Verilog/SystemVerilog knowledge and waveform-debug skills sufficient to develop custom transactors/agents.
• Strong software and automation skills: Python plus one or more of C, C++, Rust, Tcl, or shell scripting.
• Proven ability to build tools and infrastructure (not just run existing flows) and to drive reuse-first solutions.
• System-level debug instincts across RTL, firmware, and software.
• Ability to work independently and across teams.
• Authorization to work in the United States and ability to work from the Mountain View office Tuesdays–Thursdays.
• Ability to comply with U.S. export control requirements relevant to the role.

Nice-to-have

• UVM or hybrid SoC testbench development experience.
• Integrating cycle-accurate, software, or reference models into emulation/DV flows.
• Rust used in verification/emulation flows, Bazel or large-scale build/regression systems.
• Experience with connectivity subsystems: PCIe/CXL, Ethernet, DMA, HBM, chiplets, interconnect fabrics.
• Firmware or driver bring-up experience on emulation platforms and scaling emulation infrastructure.
• Experience applying AI/LLMs to build engineering tools beyond chat prompting.

Education Requirements

Not specified.

About the Company

Company: MatX

Headquarters: Mountain View, California, USA

MatX specializes in creating faster chips for large language models (LLMs), focusing on innovative hardware and software solutions. The company fosters a collaborative and supportive work environment, welcoming candidates of all experience levels. Their approach prioritizes deep understanding and consideration of novel methods to drive efficiency and performance in their projects, particularly in silicon design and related engineering roles.