Senior Staff Digital Verification Engineer, Memory Interface IP (HBM/DDR/LPDDR)
SynopsysJob Title
Senior Staff Digital Verification Engineer, Memory Interface IP (HBM/DDR/LPDDR)
Role Summary
Senior verification engineer responsible for designing and executing verification strategies for memory interface IP (HBM, DDR, LPDDR) within a verification team. Works with architects and design teams to close coverage gaps and ensure production-quality IP.
Primary mission: build reusable verification environments, drive coverage closure, and mentor engineers to reduce post-silicon issues and accelerate delivery.
Experience Level
Senior - expects approximately 6 to 8+ years of hands-on ASIC/SoC verification experience focused on interface or memory IP.
Responsibilities
Key day-to-day responsibilities:
- Design and implement verification environments for HBM, DDR, LPDDR and related interface IP using SystemVerilog and UVM.
- Write and execute detailed test plans for functional scenarios, corner cases, and protocol compliance.
- Develop reusable verification IP and adaptable testbenches across projects and IP variants.
- Collaborate with design and architecture teams to identify bugs, clarify specs, and close coverage gaps prior to tapeout.
- Run functional coverage analysis, track metrics, and drive coverage closure in multi-protocol environments.
- Mentor and coach junior verification engineers on UVM best practices, debugging, and verification strategy.
- Use commercial simulators to run regression suites, debug failures, and validate design changes.
Requirements
Must-have technical skills and experience:
- Proven experience verifying Interface IP protocols such as HBM, DDR, LPDDR, or AMBA in production designs.
- Strong proficiency in SystemVerilog and UVM including testbench development and assertions.
- Deep understanding of digital design concepts, timing, protocol compliance, and memory subsystem architecture.
- Experience using simulation tools such as VCS, ModelSim, Xcelium, or equivalents in regression and debug workflows.
- Demonstrated ability to plan and drive functional coverage closure and deliver fully verified IP on schedule.
- Ability to mentor team members and communicate complex protocol issues clearly to designers and architects.
Nice-to-have:
- Hands-on experience with HBM2/HBM3, DDR4/DDR5, or LPDDR4/LPDDR5 variants.
- Experience building highly reusable verification components across IP variants.
Education Requirements
Bachelor's or Master's degree in Electrical Engineering or Computer Engineering (as stated). The posting specifies degree-level qualifications; no certifications or "equivalent experience" language was provided.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
