Senior Staff Digital Methodology Engineer, Design-for-Testability (DFT)

Job Title

Senior Staff Digital Methodology Engineer, Design-for-Testability (DFT)

Role Summary

Lead DFT methodology definition and deployment for large-scale ASIC and SoC programs within Synopsys' Digital Methodology Center of Excellence. Act as technical lead on strategic customer engagements, translating architecture decisions into deployable best practices that improve test coverage and manufacturability.

Work spans methodology architecture, automation, product collaboration, and field deployment for advanced-node, multi-die designs.

Experience Level

Senior - requires 10+ years in the semiconductor or EDA industry, with at least 5 years focused on DFT architecture, ATPG, and manufacturing test methodologies.

Responsibilities

Primary responsibilities include defining methodologies, deploying solutions, and providing technical leadership.

• Define and drive DFT methodologies and best practices for next-generation ASIC and SoC designs.
• Lead deployment of scan compression, hierarchical DFT, IEEE 1500 wrappers, IJTAG networks, and embedded test IP across multi-billion-gate designs.
• Architect scalable test access infrastructures using IEEE 1149.1, 1149.6, 1687, and 1500 standards for multi-die and chiplet systems.
• Develop automation frameworks, signoff criteria, and reusable methodology packages using Tcl, Python, and Perl.
• Act as subject-matter expert for Synopsys TestMAX DFT and TestMAX ATPG in customer engagements and internal escalations.
• Collaborate with R&D and product teams to translate deployment challenges into product requirements.
• Provide technical leadership during methodology reviews, tapeout decisions, silicon bring-up, and diagnosis.

Requirements

Must-have skills and experience:

• 10+ years in semiconductor or EDA industry; 5+ years focused on DFT, ATPG, and manufacturing test methodologies.
• Proven experience architecting and implementing DFT solutions for large-scale ASIC/SoC designs with successful tapeouts.
• Hands-on experience with Synopsys TestMAX DFT and TestMAX ATPG in production design environments.
• Deep knowledge of scan insertion, scan compression, hierarchical DFT, ATPG and diagnosis, and fault models (stuck-at, transition, path-delay, bridge, cell-aware).
• Experience integrating DFT IP: embedded compression, OCC, LBIST, TAP controllers, JTAG/IJTAG infrastructure, TDR networks, and IEEE 1500 wrappers.
• Strong understanding of RTL-to-GDSII flows and how DFT interacts with synthesis, physical design, timing closure, and signoff.
• Proficiency in Tcl, Python, Perl, or shell scripting for methodology automation and deployment.

Nice-to-have:

• Experience defining enterprise-wide DFT standards and signoff methodologies.
• Background with advanced-node ASICs, multi-billion-gate SoCs, silicon bring-up, diagnosis, or yield improvement.
• Knowledge of functional safety and automotive test requirements.
• Contributions to industry standards, publications, patents, or conference presentations.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field (as stated in the posting).

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.