Senior Staff, Digital Methodology Engineer - Design for Testability (DFT)

Job Title

Senior Staff, Digital Methodology Engineer - Design for Testability (DFT)

Role Summary

Lead development and deployment of DFT methodologies and test access architectures for large-scale ASIC and SoC designs. Work with product R&D, customer engagements, and strategic accounts to translate architecture decisions into reusable, automated methodology packages that reduce time-to-market and improve silicon yield.

Experience Level

Senior - requires extensive experience. The posting requests 10+ years in the semiconductor or EDA industry with at least 5 years focused on DFT architecture, ATPG, and manufacturing test methodologies.

Responsibilities

Deliver methodology, automation, and technical leadership for complex DFT deployments across strategic programs.

• Define and drive DFT methodologies and signoff criteria for next-generation ASIC/SoC designs.
• Lead deployment of scan compression, hierarchical DFT, IJTAG, IEEE 1500 wrappers, and embedded test IP on multi-billion-gate designs.
• Architect test access infrastructures using IEEE 1149.1/1149.6/1687/1500 for multi-die and chiplet systems.
• Develop automation frameworks and reusable methodology packages using Tcl, Python, Perl, or Shell.
• Act as subject matter expert for TestMAX DFT/ATPG, diagnosis, and silicon lifecycle issues in customer escalations and engagements.
• Collaborate with R&D to influence product roadmap based on deployment challenges and customer requirements.
• Provide technical leadership during methodology reviews and complex architecture decisions that impact tapeout schedules.

Requirements

Key technical skills and experience required for the role.

• Must-have:
  • 10+ years in semiconductor or EDA industry with at least 5 years focused on DFT architecture, ATPG, and manufacturing test methodologies.
  • Proven experience architecting and implementing DFT solutions for large-scale ASIC/SoC designs, including successful tapeouts.
  • Hands-on experience with Synopsys TestMAX DFT and TestMAX ATPG in production design environments.
  • Deep knowledge of scan insertion, scan compression, hierarchical DFT, ATPG and diagnosis, and advanced fault models.
  • Experience deploying IEEE 1149.1, 1149.6, 1687, and 1500 standards in complex test access architectures.
  • Experience integrating DFT IP (compression codecs, OCC, LBIST, TAP controllers, IJTAG/JTAG infrastructure, TDR networks, IEEE 1500 wrappers).
  • Strong understanding of RTL-to-GDSII flows and interactions between DFT, synthesis, physical design, timing closure, and signoff.
  • Proficiency with Tcl, Python, Perl, or Shell for methodology automation and deployment.
• Nice-to-have:
  • Experience defining enterprise-wide DFT standards and signoff methodologies.
  • Background with advanced-node ASICs, multi-billion-gate SoCs, silicon bring-up, diagnosis, or yield improvement.
  • Knowledge of functional safety and automotive test requirements.
  • Contributions to industry test standards, publications, patents, or conference presentations.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field (as stated in the posting).

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.