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Senior Staff Digital Design Engineer

Synopsys
October 13, 2026
Full-time
On-site
Bengaluru, Karnataka, India
RTL Design Jobs, Level - Senior

Job Title

Senior Staff Digital Design Engineer

Role Summary

Senior individual contributor on the R&D Solutions Group at the Bengaluru Design Center responsible for architecting and delivering RTL for high-performance DDR PHY and related IP cores. The role combines hands-on RTL implementation, design ownership across the full IP lifecycle, and technical leadership of small design teams in a multi-site environment.

Experience Level

Senior - 10+ years of ASIC digital design experience (source specifies 10+ years).

Responsibilities

Primary responsibilities include end-to-end IP design execution, architecture, RTL implementation, and mentoring.

  • Lead full IP design lifecycle from architecture through delivery for DDR PHY and related IP.
  • Architect and implement state-of-the-art RTL for medium- to high-complexity features.
  • Translate specifications into architecture, micro-architecture and design documentation.
  • Perform RTL coding, lint/CDC analysis, synthesis, static timing analysis, and debug.
  • Develop and support test plans and collaborate with verification teams to resolve issues.
  • Lead and mentor small teams of RTL designers; coordinate work across global sites.
  • Propose and implement process and flow improvements for design efficiency and quality.
  • Troubleshoot and resolve complex design and verification problems to ensure robust deliverables.

Requirements

Key technical and leadership requirements. Education items are listed separately under Education Requirements.

Must-have:

  • Extensive experience with RTL design and simulation using Verilog/SystemVerilog.
  • Proven experience with design flows: lint, CDC analysis, synthesis, static timing analysis; experience with formal verification is expected.
  • Deep experience designing high-performance interface/protocol IP (examples: DDR, PCIe, USB, HBM).
  • Experience architecting control-path designs (asynchronous FIFOs, DMA, SPRAM/DPRAM interfaces).
  • Demonstrated ability to technically lead projects and mentor engineers.

Nice-to-have:

  • Familiarity with scripting (Perl, Shell) to support flows and automation.
  • Prior responsibility for full IP delivery and cross-site coordination on complex projects.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Electronics, VLSI, or a related discipline (as stated in the source).


About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.

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Date Posted: 2026-10-04