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Senior Staff DFT Engineer

Renesas
June 08, 2026
Full-time
On-site
Madison, Wisconsin, United States
DFT Jobs, Level - Senior

Job Title

Senior Staff DFT Engineer

Role Summary

Join Renesas's Infrastructure Power Business to develop mixed-signal, MCU-based power-management SoCs for datacenter applications. The role leads design-for-test (DFT) for analog and mixed-signal blocks to ensure efficient, high-coverage testability and transfer to ATE.

Work with firmware, verification, and ATE teams to deliver test methods, calibration/trim flows, and verification that tests meet parametric requirements.

Experience Level

Senior-level β€” 10 years of relevant experience.

Responsibilities

Accountable for DFT strategy, implementation, and verification for analog and mixed-signal blocks.

  • Own the test plan for analog and mixed-signal content.
  • Ensure observability and controllability of blocks to/from package pins.
  • Enable parallel on-chip testing to minimize tester interaction and test time.
  • Define test, trim, and calibration requirements for blocks such as PLLs, DLLs, ADCs, and DACs.
  • Create block test definitions and procedures suitable for ATE test generation.
  • Modify schematics and behavioral models to implement testability features.
  • Write and bench-validate firmware to exercise test routines and trim procedures prior to ATE transfer.
  • Simulate test routines across PVT and noise to demonstrate adherence to parametric specs.
  • Coordinate with design, firmware, verification, and ATE teams to ensure DFT effectiveness and correct test-hardware requirements.
  • Balance silicon area cost against test time savings when specifying DFT features.

Requirements

Must-have technical skills and practical experience.

  • Expertise in SystemVerilog for test/DFT purposes.
  • Experience with Cadence Virtuoso for analog/mixed-signal design and modification.
  • Working knowledge of C/C++ for microcontroller firmware used in test and trim routines.
  • Fundamental understanding of mixed-signal blocks (ADCs, DACs, PLLs/DLLs) and their testability.
  • Understanding of ATE tester limitations and test-time cost drivers.
  • Familiarity with firmware and ATE program structure; ability to translate DFT simulations to ATE methods (preferred).
  • Experience with lab/bench validation and transferring patterns/firmware to ATE.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering.


About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.

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Date Posted: 2026-06-08