Senior Staff DFT Engineer

Job Title

Senior Staff DFT Engineer

Role Summary

Lead Design for Testability (DFT) implementation and verification for Mythic's ASIC/SoC products, owning MBIST, IJTAG, scan, ATPG and related flows from concept through silicon. Collaborate with RTL, physical design, STA and analog teams to enable first-pass silicon success.

Mythic builds an analog compute engine for efficient AI inference at the edge; this role focuses on delivering production-quality, testable silicon.

Experience Level

Senior — 8+ years industry experience.

Responsibilities

Primary responsibilities are implementation of DFT features, establishing DFT methodology, and ensuring testability and debug capability for SoC projects.

• Lead end-to-end DFT implementation (MBIST, scan, IJTAG, ATPG, memory repair) for complex SoCs.
• Develop and integrate DFT test suites and RTL required for testability.
• Define pre-silicon test plans and verification strategies to achieve first-pass success.
• Collaborate with RTL, physical design, STA and analog teams to specify DFT timing and low-power constraints.
• Drive root-cause analysis and resolve DFT implementation and silicon bring-up issues.
• Improve and document DFT methodologies and flows across projects.

Requirements

Must-have skills and experience:

• 8+ years industry experience in SoC-level DFT.
• Practical expertise in SoC DFT methodologies: memory repair, hierarchical DFT, scan insertion, TPI, SSN, IEEE 1687 (iJTAG), and ATPG.
• Experience with DFT integration, verification, and RTL design for DFT.
• Proficiency in Verilog/SystemVerilog and DFT tools (e.g., Synopsys TetraMAX/DFT Compiler or Mentor/Tessent).
• Scripting skills for flow automation (Perl, Tcl, Python).
• Strong communication skills and ability to work in a distributed team environment.

Nice-to-have:

• Experience with AI processor designs and chiplet-based architectures.
• Knowledge of low-power DFT solutions (clock gating, power gating) and STA timing constraints.
• Experience with ATE for bring-up, debugging, and yield improvement.
• Familiarity with Cadence toolsets and Sub-10nm process experience.
• Startup experience.

Education Requirements

BS, MS, or PhD in Electrical Engineering or Electronics & Communication Engineering (EE/ECE).

About the Company

Company: Mythic

Headquarters: Austin, Texas, USA

Mythic is revolutionizing AI computing through innovative analog technology, significantly enhancing performance compared to traditional digital systems. Their cutting-edge solutions cater to demanding applications in various sectors, including industrial, automotive, and aerospace. With over $100M raised from top investors, Mythic is poised to transform AI workloads and applications.