Senior Staff Design Verification Engineer – Coherent Interconnect

Job Title

Senior Staff Design Verification Engineer – Coherent Interconnect

Role Summary

Lead verification of a scalable, cache-coherent interconnect subsystem used in high-performance SoCs. Individual-contributor role that defines verification strategy, identifies and mitigates architectural risks, and raises verification quality and reuse across teams.

Work closely with architecture, RTL, formal, and software teams to verify protocol correctness, ordering, flow control, QoS, and subsystem integration across multiple interfaces and bridge paths.

Experience Level

Senior (Senior Staff). Requires 8+ years of ASIC/SoC design verification experience.

Responsibilities

Primary responsibilities include planning, implementing, and executing verification for coherent interconnect subsystems.

• Own verification planning and execution from block-level verification through subsystem integration and signoff.
• Define verification strategy, test plans, environments, and closure criteria for coherency, ordering, flow control, buffering, QoS, and error handling.
• Develop and maintain verification environments, checkers, scoreboards, assertions, stimulus, and coverage models.
• Verify subsystem behavior across interfaces and bridge paths, including CHI, ACE, CXL, and similar coherent flows.
• Create directed and constrained-random scenarios to exercise corner cases in coherency, concurrency, credits, arbitration, and bandwidth-sensitive behavior.
• Partner with architecture, RTL, formal, and software teams to clarify specifications and close ambiguities early.
• Debug failures, isolate root cause, and drive durable fixes across RTL and verification infrastructure.
• Contribute to verification methodology and infrastructure improvements for horizontal reuse.
• Mentor engineers and raise verification quality across the team.

Requirements

Must-have skills and experience; preferred items listed below.

• 8+ years of ASIC or SoC design verification experience.
• Strong hands-on experience with SystemVerilog and building reusable verification infrastructure.
• Deep understanding of cache-coherent systems, on-chip interconnects, memory subsystem behavior, ordering, and flow-control semantics.
• Protocol knowledge in CHI, ACE, CXL, AXI, or similar coherent/high-performance interconnect standards.
• Experience creating test plans, assertions, coverage models, and debug workflows for complex hardware subsystems.
• Strong scripting and automation skills (Python or similar).
• Strong communication skills and ability to work effectively across architecture, RTL, and verification teams.

Nice-to-have:

• Experience verifying coherent interconnect, cache, or memory-subsystem IP in high-performance SoCs.
• Experience with protocol-conversion or bridge-heavy subsystems.
• Experience with formal verification, performance-oriented verification, or emulation/FPGA-assisted debug.
• Demonstrated technical leadership and ability to influence verification quality beyond immediate ownership.

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.