Senior Staff Design Verification Engineer – Coherent Interconnect

Job Title

Senior Staff Design Verification Engineer – Coherent Interconnect

Role Summary

Lead verification of a scalable, cache-coherent interconnect subsystem for high-performance SoCs. Individual-contributor role that defines verification strategy, drives subsystem-level verification and integration, and collaborates with architecture, RTL, formal, and software teams to ensure protocol correctness, ordering, flow control, QoS, and robust subsystem behavior.

Experience Level

Senior-level. Requires 8+ years of ASIC or SoC design verification experience appropriate for a Senior Staff / T5 role.

Responsibilities

Primary responsibilities include planning, executing, and improving verification for a coherent interconnect subsystem from block level through subsystem signoff.

• Own verification planning and execution for a scalable cache-coherent interconnect from block verification through subsystem integration and signoff.
• Define verification strategy, test plans, environments, and closure criteria for coherency, ordering rules, backpressure, flow control, buffering, QoS, and error handling.
• Develop and maintain verification environments, checkers, scoreboards, assertions, stimulus, and coverage models.
• Drive verification across interface boundaries and protocol adaptation layers, including CHI, ACE, CXL, AXI, and bridge paths.
• Create directed and constrained-random scenarios to expose coherency, concurrency, credits, arbitration, QoS, and bandwidth corner cases.
• Partner with architecture, RTL, formal, and software teams to resolve specification ambiguities and improve verification quality.
• Debug failures, isolate root causes, and coordinate fixes across RTL, assertions, testbench infrastructure, and test content.
• Contribute to methodology and infrastructure improvements for the broader interconnect verification effort.
• Mentor engineers and raise verification quality across the team.

Requirements

Applicants should meet the must-have technical skills and experience below; preferred items are listed separately.

Must-have:

• 8+ years of ASIC or SoC design verification experience, with depth appropriate for a Senior Staff role.
• Hands-on experience with SystemVerilog and building reusable verification infrastructure for complex hardware subsystems.
• Strong understanding of cache-coherent systems, on-chip interconnects, memory subsystem behavior, and verification of ordering and flow-control semantics.
• Protocol knowledge in CHI, ACE, CXL, AXI, or similar coherent/high-performance interconnect standards.
• Experience creating test plans, assertions, coverage models, and debug workflows for complex hardware subsystems.
• Strong scripting and automation skills in Python or similar languages.
• Effective communication and collaboration skills across architecture, RTL, and verification teams.

Nice-to-have:

• Experience verifying coherent interconnect, cache, or memory-subsystem IP in high-performance SoCs.
• Experience with protocol-conversion or bridge-heavy subsystems.
• Experience with formal verification, performance-oriented verification, or emulation/FPGA-assisted debug.
• Demonstrated technical leadership and ability to influence verification quality beyond immediate ownership.

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field is specified.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.