Senior / Staff Design Verification Engineer

Job Title

Senior / Staff Design Verification Engineer

Role Summary

Join the silicon engineering team to lead functional verification for complex next-generation SoCs and IPs. You will own verification architecture, environment development, debug, and coverage closure to deliver tape-out-ready designs.

This role focuses on SystemVerilog/UVM-based constrained-random verification, cross-team collaboration with Design and Architecture, and mentoring junior engineers.

Experience Level

Senior-level — typically requires 5+ years of ASIC/SoC design verification experience.

Responsibilities

Key responsibilities include ownership of verification plans, environment development, and driving verification closure.

• Define and author feature-driven testplans from architectural and micro-architectural specifications.
• Design, build, and maintain scalable constrained-random verification environments using SystemVerilog and UVM.
• Define verification strategies at block, subsystem, and SoC levels, using simulation and formal methods where applicable.
• Debug complex test failures, triage RTL vs testbench issues, and coordinate fixes with Design and Architecture teams.
• Implement and analyze functional and code coverage; drive the team to coverage sign-off.
• Provide technical guidance and mentorship; participate in code and testplan reviews.

Requirements

Must-have technical skills and experience.

• 5+ years of hands-on ASIC/SoC design verification experience.
• Advanced proficiency in SystemVerilog and strong OOP concepts.
• Extensive, practical UVM experience (sequences, drivers, monitors, scoreboards, predictors).
• Strong digital design fundamentals: pipelines, FIFO, memory controllers, clock/reset domains, computer architecture.
• Proven experience writing and closing complex functional and code coverage.
• Proficiency with industry-standard debug tools (e.g., Verdi, DVE) and methodical root-cause analysis.
• Familiarity with on-chip protocols such as AXI, AHB, APB, PCIe, NVMe, USB, or Ethernet.
• Scripting skills (Python, Perl, Tcl) and Shell scripting for automation.
• Strong communication, problem-solving, and ownership mindset; ability to mentor junior engineers.
• Must be eligible to work in India and pass background and reference checks; may require export-control authorization.

Education Requirements

Bachelor's or Master's degree in Electronics/Electrical/Computer Engineering or related fields (ECE, EEE, Embedded Systems, VLSI) is preferred; equivalent practical experience will be considered.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.