Senior Staff Design Engineer - Memory Subsystem COE

Job Title

Senior Staff Design Engineer - Memory Subsystem COE

Role Summary

Senior hardware design engineer responsible for micro-architecture, RTL implementation, and integration of DDR/LPDDR/HBM memory subsystems within Marvell's Center of Excellence. The role partners with architecture, verification, physical design, firmware, and validation teams to deliver production-ready IP subsystems for data center and cloud SoCs.

Experience Level

Senior — typically requires advanced hands-on RTL experience. Years guidance: Bachelor's with 5–10+ years or Master's/PhD with 3–5 years (see Education Requirements).

Responsibilities

Deliver and integrate memory subsystem IP and provide technical leadership across the design flow.

• Define subsystem micro-architecture and drive RTL implementation for DDR/LPDDR/HBM controllers.
• Translate architecture requirements into robust, PD- and DFT-friendly RTL.
• Collaborate with design verification on test plans, debug, and coverage closure.
• Partner with Physical Design and DFT teams to ensure synthesis and sign-off readiness.
• Support silicon bring-up and post-silicon debug with firmware and validation teams.
• Drive coding best practices, design quality improvements, and reuse across projects.
• Participate in design and milestone reviews and cross-functional technical discussions.
• Mentor junior designers and provide technical leadership within the memory design domain.

Requirements

Must-have technical skills and experience required for successful performance in this role.

• Proven experience delivering complex DDR, LPDDR, or HBM controllers/subsystems from architecture through RTL closure.
• Strong hands-on experience in SystemVerilog / Verilog RTL development.
• Familiarity with JEDEC DDR/HBM specifications.
• Deep knowledge of ARM-based SoC integration and AMBA protocols (AXI-4, CHI, ACE).
• Solid understanding of clocking, resets, CDC/RDC, low-power techniques, and performance optimization.
• Experience supporting lint, CDC/RDC, synthesis, and design sign-off flows.
• Experience with industry EDA tools (Synopsys, Cadence, Mentor/Siemens).
• Proficient in scripting (TCL, Perl, Python) and version control (GIT, SVN).
• Must be eligible to access export-controlled technology; candidates may be subject to export license review.

Nice-to-have:

• End-to-end DDR/HBM subsystem RTL execution and sign-off experience.
• Experience designing high-performance, low-latency datapaths and handling ordering, coherency, and error mechanisms.
• Practical post-silicon bring-up and debug experience collaborating with firmware and validation teams.
• Prior experience mentoring engineers and providing cross-functional technical leadership.

Education Requirements

Bachelor's degree in Electronics/Electrical Engineering with 5–10+ years of relevant RTL design experience; or Master's or PhD with ~3–5 years of relevant experience in RTL/ASIC/SoC design or equivalent demonstrated experience in the domain.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.