Senior/Staff Design Engineer / Architect, Datapath (HBM)

Job Title

Senior/Staff Design Engineer / Architect, Datapath (HBM)

Role Summary

The HBM Architecture team develops datapath solutions for next-generation High Bandwidth Memory (HBM) products. This role architects, designs, and optimizes high-speed datapath circuitry across logic and core dies to deliver bandwidth, power efficiency, reliability, and scalability.

The engineer will collaborate with PHY, ECC, verification, layout, and system teams to take designs from concept through silicon bring-up and production.

Experience Level

Senior-level. See Education Requirements for degree and years-of-experience guidance.

Responsibilities

Design and deliver robust high-speed datapath architectures and implementations for HBM products.

• Architect and design HBM read/write datapaths across core and logic die, including alignment, buffering, timing, and control logic.
• Develop high-speed, low-latency datapath circuits for multi-channel HBM and wide internal buses.
• Optimize datapaths for bandwidth, power, area, and timing closure at advanced nodes.
• Design and integrate data reliability features (parity, ECC hooks, lane redundancy, remapping).
• Translate specifications into micro-architectures and drive schematic- and RTL-level implementations, including clocking, gating, and reset strategies.
• Collaborate with PHY, DFT, verification, and layout teams to ensure functionality, testability, and manufacturability.
• Participate in design reviews, documentation, and technical mentoring across HBM programs.
• Leverage AI tools to increase efficiency in routine design tasks.

Requirements

Must-have technical skills and hands-on experience.

• Experience in high-speed digital datapath design (memory, SerDes, or SoC datapath).
• Hands-on experience with digital schematic build, RTL, or mixed-signal datapath implementations.
• Proven ability to implement RTL- and schematic-level datapath blocks with attention to clocking, gating, and reset strategies.
• Experience optimizing designs for timing closure and cross-team integration with PHY, verification, and layout.
• Ability to design and integrate data reliability mechanisms (parity, ECC hooks, remapping, redundancy).
• Strong collaboration and communication skills for cross-functional design interactions.

Nice-to-have:

• Understanding of HBM/DRAM architectures, multi-channel operation, and data flow.
• Working knowledge of layout and floorplanning for high-speed datapaths.
• Experience with static timing analysis (STA) and timing-closure methodologies.
• Familiarity with advanced process-node signal integrity, skew control, and power optimization challenges.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field (or equivalent) noted; the posting specifies degree + experience tradeoffs: Bachelor's with 6+ years of relevant industry experience, or Master's with 4+ years. Equivalent practical experience is accepted. No specific certifications were listed.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.