Senior Staff ASIC Digital Design Engineer

Job Title

Senior Staff ASIC Digital Design Engineer

Role Summary

Responsible for RTL architecture, design, and delivery of high-speed protocol and Ethernet IP cores (100G–1.6T) within the DesignWare IP group. Works as a technical individual contributor on a multi-site team to produce production-quality IP that meets timing, latency, power, and safety requirements.

Collaborates with verification, integration, and product teams globally to drive micro-architecture, timing closure, and documentation for shipped silicon.

Experience Level

Senior — requires 8+ years of ASIC/IP design experience with a Bachelor's degree or 6+ years with a Master's degree.

Responsibilities

Key responsibilities include:

• Design and implement RTL for high-speed Ethernet and interconnect IP (100G–1.6T), focusing on low latency and timing closure.
• Translate protocol specifications into micro-architecture and detailed design documents for Ethernet, AMBA (AXI/CHI), PCIe, USB, MIPI, and memory controller domains.
• Develop and refine directed Verilog/SystemVerilog testbenches; analyze coverage and define targeted tests to catch silicon-relevant bugs.
• Perform technical reviews of functional specs, micro-architecture documents, and RTL across global design teams.
• Drive timing analysis and closure using synthesis, static timing analysis (STA), lint, CDC, and formal verification flows.
• Apply low-power design methodologies and automotive safety requirements where applicable.
• Collaborate with verification, integration, and product teams across sites to deliver production-quality IP on schedule.

Requirements

Must-have technical skills and experience:

• Deep RTL design experience on IP cores or SoC subsystems that have taped out or shipped to customers.
• Strong working knowledge of at least one protocol family: AMBA (AHB, AXI, CHI), SD, eMMC, DDR, PCIe, USB, or MIPI. High-speed Ethernet (100G+) is a strong plus.
• Proven ability to create micro-architecture and detailed design documents, especially for control-path blocks (async FIFOs, DMA engines, SRAM/DPRAM interfaces).
• Hands-on experience with Verilog or SystemVerilog, simulation tools, synthesis flows, STA, lint, CDC, and formal verification tools.
• Solid understanding of high-speed, low-latency design techniques and timing closure; datapath and arithmetic algorithm experience (e.g., FEC) is a plus.
• Familiarity with Perforce or similar version control systems and scripting in Perl or shell for automation.

Education Requirements

Bachelor's degree in Electrical Engineering with 8+ years of ASIC/IP design experience, or a Master's degree with 6+ years of experience. No other degree fields or certifications were specified in the source.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.