Senior / Staff ASIC Digital Design Engineer

Job Title

Senior / Staff ASIC Digital Design Engineer

Role Summary

Responsible for ASIC digital implementation focusing on DFT, synthesis, timing, and power sign-off to support tapeout milestones for SoC and memory-related designs. Works on the ASIC implementation team and collaborates with RTL, PNR, verification, and test teams to automate flows and ensure high-quality deliveries.

Experience Level

Senior-level. Typical candidates have 8+ years of relevant ASIC digital design experience; candidates with advanced degrees may be considered with approximately 6+ years.

Responsibilities

Primary responsibilities include implementation, sign-off, and test planning for ASIC blocks and full-chip designs.

• Drive DFT planning and integration; manage ATPG and ATE interfaces and support ATE bring-up and failure analysis.
• Develop and maintain full-chip and block constraints and perform static timing analysis (STA).
• Lead synthesis, formal equivalence checks, and timing closure; coordinate with RTL teams for quality RTL delivery.
• Implement DFT across multi-power-domain designs and support UPF-based low-power flows.
• Perform power and IR analysis and work with PNR on power-intent and physical implementation requirements.
• Troubleshoot synthesis, timing, DFT, and power issues and drive flow improvements and automation.
• Maintain scripts, documentation, IP design kits, and SoC sign-off checklists.

Requirements

Must-have technical skills and practical experience.

• Extensive experience with front-end and sign-off tool flows (e.g., Synopsys PrimeTime, Design Compiler, VCLP, Formality, PrimeClosure/PrimePower, VCS, VC-SpyGlass-DFT).
• Experience with Siemens Tessent, Tetramax, or equivalent DFT/ATPG tool suites.
• Proven participation in multiple tapeouts and chip deliveries.
• Low-power design experience and familiarity with UPF-based flows.
• Strong scripting skills (Tcl/Perl/Python/Shell) and familiarity with UNIX/Linux environments; AI-assisted flow experience is a plus.
• Ability to work independently, follow structured workflows, and collaborate across design, PNR, and test teams.
• Nice-to-have: experience with advanced process nodes (7nm, 5nm), voltage-drop/XTalk analysis, ATE failure analysis and yield improvement, CDC/RDC/lint checks, floorplan and timing-driven placement, and clock-tree synthesis.

Education Requirements

Bachelor's degree in Engineering with 8+ years of related experience, or Master's degree in Engineering with 6+ years of related experience (as stated in the source). The posting lists "Engineering" degrees; no other specific fields or certifications were specified.

About the Company

Company: SK hynix America

U.S. subsidiary of SK hynix, a global semiconductor company specializing in DRAM and NAND flash memory and related memory solutions for mobile devices, data centers, and consumer electronics. Focuses on advanced memory technologies, AI applications, and high-performance storage.