Senior Staff ASIC Digital Design Engineer

Job Title

Senior Staff ASIC Digital Design Engineer

Role Summary

Lead RTL design and delivery of automotive digital IP (PCIe, DDR, UCIe) intended for ISO 26262 ASIL D systems. Work across design, safety qualification, verification, and synthesis teams to produce production-quality, safety-compliant controllers.

This role combines hands-on RTL implementation and debug with technical leadership and mentorship to improve design quality, verification coverage, and automation.

Experience Level

Senior — typically requires 8+ years of relevant experience.

Responsibilities

Deliver and own RTL for automotive IP and ensure successful qualification and tapeout.

• Design and own synthesizable RTL for automotive digital IP blocks (PCIe, DDR, UCIe).
• Lead RTL coding, lint and CDC analysis, synthesis optimization, and debug of complex subsystems.
• Collaborate with verification to define VIP scope, identify coverage gaps, and close critical fault scenarios before tapeout.
• Drive safety qualification activities including DFMEA, FMEDA, and DFA for IP targeting ASIL D.
• Mentor and guide engineers on coding standards, design flows, and best practices for Verilog/SystemVerilog.
• Introduce and evaluate AI-driven design tools and automation to improve quality and reduce cycle time.

Requirements

Must-have technical skills and experience for immediate productivity in this role.

• Proven IP-level experience with high-speed protocols such as PCIe, DDR, or UCIe (PCIe strongly preferred).
• Strong RTL implementation skills in synthesizable Verilog/SystemVerilog for ASIC design and simulation.
• Experience qualifying hardware to ISO 26262 functional safety levels up to ASIL D and working knowledge of DFMEA, FMEDA, and DFA.
• Deep understanding of ASIC design flows: lint, CDC, synthesis, synthesis QoR, Static Timing Analysis, and formal verification.
• Demonstrated ability to lead as an individual contributor while mentoring and coordinating engineering teams through design and debug.
• Track record collaborating with verification teams to close feature and fault-coverage gaps.

Nice-to-have:

• Experience applying AI-driven design tools and writing reusable automation/scripts for design teams.

Education Requirements

Bachelor's degree (with ~8+ years' relevant experience) or Master's degree (with ~6+ years' relevant experience) in a relevant engineering or technical discipline, or equivalent practical experience in Automotive SoCs or digital IP development.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.