Marvell Technology logo

Senior Staff Analog Mixed-Signal Design Engineer

Marvell Technology
July 04, 2026
Full-time
On-site
Santa Clara, California, United States
$147,830 - $221,400 USD yearly
Semiconductor IP Jobs, Level - Senior

Job Title

Senior Staff Analog Mixed-Signal Design Engineer

Role Summary

Senior engineer on Marvell's Central Engineering analog IP team responsible for designing high-speed, low-power analog mixed-signal circuits for SerDes die-to-die communication and high-speed wireline products. The role involves hands-on circuit design, guiding layout and validation, and collaborating with cross-functional teams to deliver silicon-ready IP.

Experience Level

Senior — typically 7+ years of experience in analog mixed-signal design.

Responsibilities

Primary responsibilities include end-to-end design, verification, and validation of analog mixed-signal blocks and supporting cross-functional project execution.

  • Design and develop high-speed, low-power analog mixed-signal circuits in advanced CMOS technologies, focusing on SerDes and high-speed wireline applications.
  • Design analog blocks such as clock generation/distribution, DLLs, CTLE, VGA, TX drivers, ADCs, DACs, regulators, and custom high-speed digital circuits.
  • Supervise and guide layout activities to meet performance, area, and reliability targets.
  • Perform post-silicon testing, debugging, and characterization in the lab to validate circuit performance.
  • Use EDA tools for schematic capture, simulation, layout, and verification; prepare design documentation and participate in design reviews.
  • Collaborate with system, verification, reliability, and software teams to ensure successful project delivery.

Requirements

Key technical qualifications and skills required for the role.

  • 7+ years of demonstrated experience in analog mixed-signal design, including ADCs, DACs, regulators, clock circuits, DLLs, CTLE, VGA, and TX drivers.
  • Proven expertise in high-speed and low-power design trade-offs and optimization in advanced CMOS processes.
  • Experience overseeing layout engineers and ensuring layouts meet design specifications.
  • Hands-on post-silicon validation experience with lab equipment for debugging and characterization.
  • Strong understanding of CMOS process technology, device physics, and process variation effects.
  • Proficiency with industry EDA tools (e.g., Cadence, Synopsys, Mentor Graphics) for schematic, simulation, layout, and verification.
  • Effective communication, presentation, and documentation skills; ability to lead design reviews.
  • Nice-to-have: experience with SerDes/optical products, system-level integration, or prior leadership of multi-disciplinary design teams.

Education Requirements

Posting specifies an MS or PhD in Electrical Engineering. The listing pairs this degree expectation with 7+ years of analog mixed-signal design experience.


About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.

Marvell Technology logo

Date Posted: 2026-07-04