Principal SoC DFT Engineer, HBM

Job Title

Principal SoC DFT Engineer, HBM

Role Summary

Lead DFT architecture, implementation, and signoff for HBM base-die System-on-Chip (SoC) designs within the Heterogeneous Integration Group. Work across RTL, verification, physical design, and product engineering to deliver testable, manufacturable SoC solutions from pre-silicon through tapeout and product bring-up.

Experience Level

Senior — 7+ years of relevant experience in SoC design, DFT, or implementation for complex digital ASICs/SoCs.

Responsibilities

Primary responsibilities include defining and delivering DFT features and flows at the SoC level, and coordinating across teams for signoff and silicon bring-up.

• Own SoC-level DFT implementation: scan, MBIST/LBIST, boundary scan (JTAG), and test access architecture for HBM base-die designs.
• Define DFT architecture early, aligning with integration, floorplanning, timing, power, and physical constraints.
• Implement and integrate DFT logic at block, subsystem, and full-chip levels with RTL and integration teams.
• Execute DFT flows and signoff: lint, CDC, DFT rule checks, ATPG readiness, and coverage closure.
• Collaborate with physical design for placement, routing, timing closure, and DRC/LVS considerations.
• Support pre-silicon debug and post-silicon bring-up, testability, diagnosability, and yield/debug analysis.
• Partner with CAD and methodology teams to standardize and improve DFT flows across programs.

Requirements

Must-have technical skills and domain experience.

• Proven experience in DFT for large, complex SoCs and ASICs, including multi-IP integration.
• Hands-on knowledge of scan insertion, MBIST/LBIST architectures, boundary scan (JTAG), and ATPG concepts.
• Familiarity with full RTL-to-GDS flows and interactions between DFT, synthesis, STA, and physical design.
• Experience with industry-standard EDA tools (Siemens, Synopsys, Cadence) for DFT and implementation.
• Proficiency with scripting languages for flow automation (Python, Tcl, Perl, etc.).
• Experience executing DFT signoff, coverage closure, and readiness checks for tapeout.
• Strong collaboration skills with verification, product engineering, test, probe, and manufacturing teams.

Education Requirements

Bachelor’s degree or higher in Electrical Engineering, Computer Engineering, or a related technical field.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.