The position involves planning, building, and executing the verification of new and existing features for AMD’s SERDES IP. Ensuring that the final design is free of bugs is a critical focus of this role.
This is a senior-level position that requires extensive expertise in analog design.
Candidates should possess substantial experience in high-speed analog design, particularly with blocks like ADCs, PLLs, and related technologies. Familiarity with advanced process technologies, such as 7nm FinFET technology, is required.
A Bachelor’s, Master’s, or Ph.D. degree in Electronic Engineering is required.