Senior Staff Analog Design Engineer

Job Title

Senior Staff Analog Design Engineer — SerDes/High-Speed Interfaces

Role Summary

Design analog front-end blocks for SerDes and other high-speed interfaces and take ownership from specification through silicon bring-up. Collaborate with layout, digital RTL, verification, and characterization engineers to deliver production-quality IP.

Focus on meeting performance, power, and reliability targets for multi-gigabit links used in AI accelerators, data center switches, automotive SoCs, and consumer devices.

Experience Level

Senior-level. Typical background: PhD +2 years in SerDes/high-speed analog design, or BTech/MTech with 5–10 years of relevant experience.

Responsibilities

Key responsibilities include:

• Design and optimize analog front-end building blocks (voltage/current-mode drivers, equalizers, CDRs, PLLs/DLLs, VCOs, phase interpolators, bandgaps, regulators).
• Run SPICE simulations across PVT corners and develop verification test benches to validate performance against protocol specifications.
• Collaborate with layout engineers to minimize parasitics, reduce mismatch, and account for proximity effects in sub-micron CMOS processes.
• Integrate and verify calibration loops, adaptation algorithms, and control logic with digital RTL teams.
• Present simulation results, design tradeoffs, and performance data in peer reviews and customer technical discussions.
• Document circuit architecture, verification strategies, and test plans; support post-layout verification and silicon characterization.
• Ensure design-for-reliability checks for electromigration, IR drop, aging, and ESD.

Requirements

Must-have skills and experience:

• Silicon-proven experience delivering analog or mixed-signal blocks in production chips.
• Deep expertise in multiple SerDes/high-speed building blocks (analog front-ends, drivers, PLLs/CDRs, equalizers, serializers/deserializers, impedance calibration, phase interpolation).
• Strong SPICE simulation skills and experience with sub-micron CMOS design methodologies, corner setup, parameter sweeps, and result interpretation.
• Proven experience optimizing layout for performance, including parasitic extraction and device matching.
• Proven ability to collaborate across layout, digital, verification, and characterization teams and communicate technical results clearly.
• Nice-to-have: scripting for automation (TCL, Perl) and familiarity with high-speed serial standards (PAM4, PCIe 6.0/7.0, Ethernet, USB, SATA, HDMI, MIPI).

Education Requirements

PhD with 2+ years of hands-on SerDes or high-speed analog design experience, or BTech/MTech with 5–10 years in the same domain. Relevant fields include Electrical/Electronics/Analog/Mixed-Signal engineering or closely related technical disciplines. Equivalent practical experience is implied by the requirement for silicon-proven experience.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.