Senior Staff Analog Design Engineer

Job Title

Senior Staff Analog Design Engineer

Role Summary

Join the Central Engineering – Optical PHY (CE-OPHY) team to design high-speed and optical transceivers for long-haul, metro and datacenter communication systems. The role focuses on transistor-level analog design, layout supervision, modeling and post-layout verification for multi-GHz to multi-tens-of-GHz transceivers using advanced CMOS nodes.

Experience Level

Senior. See Education Requirements for degree-based experience thresholds and required years of relevant work experience.

Responsibilities

Design and deliver analog building blocks for high-speed optical transceivers and support their integration and validation.

• Develop high-performance analog or DSP-based transceiver blocks operating in the multi-tens of GHz range.
• Analyze block specifications and select appropriate topologies and architectures.
• Design analog circuits at the transistor level and produce design documentation.
• Supervise custom layout activities, provide layout guidelines, and perform post-layout verification.
• Create and validate behavioral and device models; correlate simulations with silicon measurements.
• Collaborate with other teams to improve solutions and support system-level integration.
• Train, mentor and review work of junior designers.

Requirements

Core technical skills and language/eligibility requirements.

• Proven experience owning IC design blocks from architecture through lab characterization.
• Strong analog transistor-level design experience, preferably in the multi-GHz frequency range.
• Extensive experience performing or supervising custom analog layout and familiarity with layout-for-test and DRC/LVS flows.
• Proficiency with EDA/CAD tools for schematic, simulation, layout and post-layout verification.
• Experience measuring IC performance, debugging silicon, and correlating measurements with simulation models.
• Strong written and verbal communication, presentation and documentation skills.
• Proficiency in both spoken and written Italian and English (B2 level or higher).
• May require eligibility for access to export-controlled technology; candidates must meet applicable export control requirements.
• Preferred: direct project experience with multi-Gbps electrical SerDes or electro-optical transceivers and advanced CMOS nodes (FinFET, deep-submicron processes).

Education Requirements

Master's degree in Electrical Engineering (preferably Microelectronics) with 6+ years of relevant experience, OR PhD in Electrical Engineering (preferably Microelectronics) with 3+ years of relevant experience. Related technical degrees or equivalent practical experience are acceptable where demonstrated. Language and export-eligibility expectations apply as noted above.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.