Senior STA Signoff Methodology Engineer

Job Title

Senior STA Signoff Methodology Engineer

Role Summary

Lead development and deployment of static timing analysis (STA) sign‑off strategies and methodologies for NVIDIA GPUs, CPUs, LPUs and SoCs. The role focuses on modeling advanced-node physical effects, improving STA-to-silicon correlation, and creating automation and tools that improve performance, yield, and reliability.

Experience Level

Senior-level — typically 8+ years of experience in ASIC design and timing.

Responsibilities

Work across signoff, timing, and physical design teams to define and implement timing‑signoff flows and analysis.

• Run large-scale SPICE simulations and STA experiments to model timing impact of advanced technologies.
• Develop STA and place-and-route (PNR) flows and recommendations addressing aging, self-heating, thermal effects, IR drop, electromigration, and other physical effects.
• Collaborate with technology leads, physical-design and timing engineers to deploy sign-off strategies for silicon delivery.
• Create tools and methodologies to extend or automate EDA capabilities for performance, predictability, and reliability.
• Perform data analysis to improve STA-to-silicon correlation using Python, JMP, or similar tools.
• Work on constraints, timing and power optimization across the flow.

Requirements

Must-have technical skills and hands-on experience.

• Solid understanding of RC extraction, device physics, STA methodologies, and EDA-tool limitations.
• Strong foundation in the mathematics and physics underlying electrical design.
• Experience with low-power techniques: multi-Vt, clock gating, power gating, activity-based power analysis, DVFS, and CDC considerations.
• Familiarity with signal and power integrity issues: crosstalk, electromigration, noise, OCV, timing margins, clock jitter, and IR drop.
• Knowledge of standard-cell, memory, and I/O IP modeling and their use in ASIC flows.
• Hands-on experience with advanced FinFET and emerging CMOS technologies at 5 nm, 3 nm, 2 nm and beyond.
• Familiarity with industry-standard tools such as PrimeTime, ICC2, RedHawk, and Tempus.
• Strong communication skills and collaborative working style.

Nice-to-have:

• Experience with 3D IC integration, die stacking and packaging, and their impact on timing closure.
• Proficiency in scripting and programming: Python and Tcl preferred; C++ is a plus.
• Advanced data-analysis and modeling skills (Python, JMP, or similar).

Education Requirements

MS in Electrical Engineering or Computer Engineering preferred; equivalent practical experience is explicitly accepted. The posting references degree-level preference alongside equivalent experience.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.