Senior STA Engineer

Job Title

Senior STA Engineer

Role Summary

Lead block-level digital synthesis and static timing analysis (STA) efforts for complex SoC blocks. Drive timing closure, power optimization and signoff quality, provide technical direction to designers, and mentor junior engineers within the digital implementation team.

Work focuses on timing constraints, timing closure across IP/subsystem/full-chip, and cross-functional collaboration with synthesis, place-and-route and verification teams.

Experience Level

Mid-level — approximately 4–6 years of relevant experience in synthesis and STA.

Responsibilities

Core responsibilities include:

• Develop and maintain complex timing constraints for IP, subsystems and full-chip designs.
• Perform static timing analysis and lead timing-closure activities across design stages.
• Analyze timing violations, identify root causes and propose practical fixes.
• Execute timing ECOs using automated tool flows and manual techniques.
• Integrate synthesis, STA, LEC and power/PD tool flows; verify liberty models including power attributes.
• Automate timing analysis and flows using Tcl/Perl/Python scripting.
• Collaborate with RTL designers, physical implementation and verification teams to resolve timing and timing-DRC issues.
• Prepare signoff STA for high-speed SoC designs in advanced process nodes (16nm and below).

Requirements

Must-have and preferred skills:

• Must-have: Hands-on experience in timing constraints development and STA for complex digital blocks; strong timing-analysis and timing-closure track record.
• Must-have: Practical experience optimizing digital designs for power and understanding of liberty models with power attributes.
• Must-have: Proficiency in Tcl/Perl/Python for automation of timing flows.
• Must-have: Familiarity with synthesis, STA, LEC and power/PD tool commands and constructs.
• Must-have: Strong troubleshooting and root-cause analysis skills for timing issues.
• Preferred: Experience with floorplanning, placement, CTS, routing, extraction, physical verification and EM/IR flows.
• Preferred: Hands-on experience with DFT/scan modes and timing.
• Willingness to travel up to 10% of the time.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering or a related technical field, or equivalent practical experience.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.