Senior STA Engineer

Job Title

Senior STA Engineer

Role Summary

Join NVIDIA's silicon implementation team as a Physical Design and Timing (STA) engineer focused on timing analysis, timing closure, and signoff quality for complex ASIC and SoC designs. You will collaborate with physical design, front-end design, methodology, and CAD teams to achieve robust block- and full-chip implementation at advanced process nodes.

Experience Level

Senior - typically requires 5+ years of relevant experience in ASIC or SoC physical design, timing analysis, or implementation.

Responsibilities

Primary responsibilities include timing signoff, closure activities, and improving timing methodology and automation.

• Drive static timing analysis and timing closure for block and full-chip designs.
• Develop, review, and debug timing constraints, scenarios, and signoff checks.
• Analyze setup, hold, noise, and variation-related timing issues and drive closure with cross-functional teams.
• Partner with physical design engineers on floorplan, CTS, routing, ECOs, and convergence activities.
• Review timing reports, identify root causes of violations, and recommend high-quality fixes with minimal design impact.
• Improve timing methodology, automation, and debug efficiency using scripting (Tcl, Perl, Python).

Requirements

Must-have technical skills and experience.

• 5+ years of experience in ASIC/SoC physical design, timing analysis, or implementation.
• Strong understanding of static timing analysis fundamentals, timing constraints, and timing closure processes.
• Hands-on experience with industry-standard EDA tools such as PrimeTime, ICC2, Innovus, Tempus, or equivalents.
• Experience debugging setup/hold violations, clocking issues, and ECO impacts.
• Solid scripting skills in Tcl and familiarity with Perl or Python for automation and debug.
• Effective communication and ability to work across design, CAD, and verification teams.

Nice-to-have:

• Advanced-node implementation and signoff experience.
• Knowledge of MMMC flows, SI, OCV/AOCV/POCV, and power-aware timing analysis.
• Track record improving timing methodology or developing reusable automation.

Education Requirements

B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or equivalent practical experience (the posting explicitly permits equivalent experience in lieu of degree).

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.