Senior SRAM Layout Design Engineer

Job Title

Senior SRAM Layout Design Engineer

Role Summary

Senior individual contributor responsible for end-to-end physical layout of SRAM and memory IP in advanced CMOS nodes. Lead mask-level layout from floorplanning through DRC/LVS-clean tapeout and collaborate closely with circuit design, physical design, integration, CAD, and foundry teams.

Experience Level

Senior — requires extensive experience (listed as 10+ years of custom IC layout experience, including 5+ years focused on SRAM or full-custom memory IP).

Responsibilities

Deliver high-quality memory layouts and improve layout methodology and automation:

• Manage custom layout for bitcell arrays, periphery, test structures, and memory macros.
• Develop and optimize floorplans, power grids, routing channels, and macro assembly for SRAM blocks.
• Perform and debug DRC, LVS, ERC, antenna, and related physical verification checks (Calibre, ICV, or similar).
• Support EM/IR review, power integrity, density/fill, DFM, dummy insertion, and layout-dependent effects closure for tapeout.
• Convert schematics into layouts with correct matching, symmetry, shielding, and parasitic constraints.
• Work with PnR and integration teams to resolve top-level DRC/LVS, pin-access, boundary, routing, and macro-integration issues.
• Implement and maintain reusable layout methodologies, checklists, and quality standards for memory IP delivery.
• Collaborate with foundry, CAD, and methodology teams on rule interpretation, waivers, and advanced-node process constraints.
• Review layouts, mentor junior engineers, and raise team execution quality.

Requirements

Core qualifications and technical skills required; followed by valuable additions.

• Must-have: 10+ years of custom IC layout experience, including 5+ years in SRAM, memory compiler, or full-custom memory IP layout.
• Must-have: Hands-on experience with advanced CMOS nodes (FinFET/GAA), preferably 5nm, 3nm or smaller.
• Must-have: Extensive Cadence Virtuoso experience for custom layout creation and review.
• Must-have: Extensive experience debugging physical verification with Calibre, ICV, or equivalent.
• Must-have: Strong floorplanning, block routing, macro assembly, pin planning, and top-level physical verification skills.
• Must-have: Practical knowledge of layout-dependent phenomena (LOD), matching, symmetry, shielding, electromigration, IR drop, and DFM considerations.
• Must-have: Effective cross-functional collaboration and clear communication; ability to mentor junior engineers.
• Nice-to-have: Scripting experience (Cadence SKILL, Python) for layout automation, checks, and reporting.
• Nice-to-have: Deep familiarity with EM/IR analysis, reliability closure, density/fill strategies, and DFM/post-processing closure at IP and top level.

Education Requirements

Specifies a BSEE or equivalent practical experience. Equivalent technical experience in lieu of degree is accepted.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.