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Senior Software R&D Engineer, ECO Route - VLSI EDA

NVIDIA
September 14, 2026
Full-time
On-site
California, CA, United States
$168,000 - $310,500 USD yearly
EDA Jobs, Level - Senior

Job Title

Senior Software R&D Engineer, ECO Route - VLSI EDA

Role Summary

Join an internal EDA research and development team that builds high-performance physical-design algorithms and tools for advanced silicon. The role focuses on ECO routing and physical optimization to support timing, power, and manufacturability for next-generation GPUs, CPUs, and accelerators.

Experience Level

Senior - typically requires 5+ years of relevant experience.

Responsibilities

Deliver research-grade algorithms and production-quality implementations spanning routing, ECOs, and cross-domain physical optimization.

  • Develop incremental physical-design technology for rapid, DRC- and parasitic-aware logic changes, including all-layer and metal-only ECOs.
  • Invent and implement detailed-routing algorithms that handle discrete and continuous optimization under advanced design rules.
  • Design cross-domain optimization tools that coordinate logic, timing, clocks, testability, power distribution, placement, routing, and DRCs.
  • Own problems end-to-end: algorithm invention, implementation, validation, and production deployment.
  • Work closely with hardware and platform teams to validate algorithms on real designs and manufacturing constraints.

Requirements

Must-have technical skills, system knowledge, and deployment readiness.

  • Strong C++ expertise and experience building high-performance software (complexity analysis, data structures, memory efficiency).
  • Deep knowledge of detailed routing: advanced design rules, pin access, route optimization, and DRC-aware implementation.
  • Familiarity with clock distribution, design-for-test (DFT), and power-delivery interactions with ECOs.
  • Proven algorithm development skills for combinatorial and numerical optimization problems.
  • Authorization to work with export-controlled technical data relevant to CPUs, GPUs, LPUs, or communications networks.
  • Experience deploying research code into production-quality flows and validating at scale.
  • Nice-to-have: experience with logic/physical co-optimization, SAT solvers, placement/legalization, IR drop mitigation, or applying ML (LLMs, RL, GNNs) to physical design or combinatorial optimization.

Education Requirements

MS or PhD preferred, or equivalent practical experience; the posting explicitly lists "MS, PhD, or equivalent experience." No specific field-of-study was mandated in the source text beyond domain relevance to physical design/EDA.


About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.

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Date Posted: 2026-09-14