Senior SOC Timing Engineer

Job Title

Senior SOC Timing Engineer

Role Summary

Responsible for timing closure and signoff for FPGA/SoC and subsystem designs. Performs static timing analysis, derives interface timing constraints, and collaborates with design, architecture, and physical design teams to achieve timing convergence and final signoff.

Experience Level

Senior - requires 10+ years of experience in timing closure and signoff.

Responsibilities

Primary duties include static timing analysis, constraint generation, and coordinating final timing signoff across teams.

• Perform static timing analysis and complete timing signoff for FPGA/SoC and subsystems.
• Provide and derive interface timing constraints for design partitions.
• Collaborate with design and architecture teams on timing convergence analysis.
• Work with physical design and PNR teams to achieve timing closure.
• Prepare timing signoff documentation and support design reviews.

Requirements

Must-have technical skills and professional attributes.

• Proficient with industry-standard static timing tools such as Synopsys PrimeTime / PTPX.
• Strong knowledge of physical design and place-and-route (PNR) flow.
• Experience with timing signoff at 10nm or smaller technology nodes.
• Strong communication, problem solving, and analytical skills.

Education Requirements

BE, MS, or PhD in Electronics / Electrical Engineering.

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.