Senior SoC STA Engineer

Job Title

Senior SoC STA Engineer

Role Summary

Senior engineer responsible for chip-level static timing analysis (STA) and timing sign-off for next-generation SoCs. The role partners with RTL, physical design, DFT, verification, product engineering, and EDA vendors to drive timing closure from early design through tape-out.

Hands-on position focused on STA methodology, constraint development, automation, timing closure, and pre-/post-silicon timing correlation.

Experience Level

Senior-level — typically 10+ years of relevant hands-on STA and timing sign-off experience.

Responsibilities

Primary responsibilities for chip-level STA ownership and timing closure:

• Own end-to-end chip-level static timing analysis and sign-off across all modes, process corners, voltages, and temperatures.
• Develop, maintain, and validate sign-off-quality SDC constraints for clocks, resets, high-speed I/O, DFT, and configuration logic.
• Drive timing closure at block and full-chip levels via critical path analysis, ECOs, and collaboration with physical design on floorplanning, placement, CTS, routing, and optimization.
• Perform advanced multi-mode multi-corner (MMMC) timing analysis including clock-domain crossing and variation-aware methodologies (OCV/AOCV/POCV).
• Lead signal integrity and crosstalk analysis, identify noise-induced timing issues, and coordinate mitigations.
• Conduct pre- and post-silicon timing correlation and manage tape-out timing sign-off readiness.
• Define and enhance organization-wide STA methodologies, sign-off standards, and automation infrastructure.
• Build and maintain STA automation and reporting flows using Python and Tcl for regressions, QoR analysis, and sign-off reporting.
• Interface with EDA vendors to evaluate tools, drive improvements, and improve flows and productivity.
• Mentor junior engineers and contribute to technical documentation and best practices.

Requirements

Essential technical skills and experience; listed as must-have and nice-to-have.

Must-have:

• 10+ years of hands-on experience owning chip-level STA and timing sign-off with multiple tape-outs at advanced nodes (22nm or below).
• Deep expertise with industry STA tools (e.g., Cadence Tempus) and advanced timing sign-off flows.
• Proven experience developing and managing complex hierarchical SDC constraints for large SoCs with multiple clock and power domains.
• Strong understanding of MMMC analysis, OCV/AOCV/POCV, signal integrity, crosstalk, and power-aware timing methodologies.
• Solid knowledge of logic synthesis and physical design methodologies, including floorplanning, power planning, CTS, place-and-route, and timing closure.
• Practical experience with CPF/UPF power intent handling in timing flows.
• Strong scripting and automation skills in Python and/or Tcl.
• Familiarity with foundry PDKs, Liberty timing models, and variation/noise modeling techniques.
• Experience with DFT timing analysis (scan, MBIST, JTAG) and collaborating across cross-functional teams and EDA vendors.

Nice-to-have:

• Prior experience mentoring teams and improving organizational STA methodologies and automation frameworks.
• Experience driving tool qualification, evaluating new EDA capabilities, or contributing to vendor tool improvements.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical discipline required; Master’s degree preferred.

About the Company

Company: InnoPhase IoT

Headquarters: San Diego, California, United States

InnoPhase IoT is a dynamic company dedicated to harnessing cutting-edge technology within a collaborative environment. They emphasize innovation and creativity, providing opportunities for employees to work on diverse projects and celebrate their successes. With a focus on excellence, InnoPhase IoT is looking for talented individuals eager to contribute to a small yet powerful team.