Senior SoC Power Analysis & Optimization Engineer

Job Title

Senior SoC Power Analysis & Optimization Engineer

Role Summary

Work on power estimation, analysis, and optimization for AI accelerator SoCs. You will partner with architects, RTL designers, and physical design teams to define power targets, perform pre- and post-layout analysis, and drive cross-functional power reduction efforts.

Experience Level

Senior — typically 8+ years of relevant industry experience.

Responsibilities

Key responsibilities include analysis, modeling, automation, and cross-team recommendations to reduce SoC power while meeting performance targets.

• Develop and maintain power estimation and energy modeling methodologies for architectural exploration and design trade-offs.
• Perform RTL, gate-level, and post-layout power analysis across SoC subsystems (compute, memory, interconnect, PCIe, HBM, clock/reset).
• Analyze AI workloads and define representative sign-off scenarios and workloads for coverage.
• Identify static and dynamic power reduction opportunities and drive optimization across teams.
• Collaborate with microarchitecture, RTL, and physical-design teams to evaluate implementation trade-offs and implement power-efficient changes.
• Develop automation, scripts, dashboards, and heuristics to accelerate analysis and root-cause investigations.
• Present analysis results and recommendations to cross-functional stakeholders.

Requirements

Must-have technical skills, experience, and constraints.

• 8+ years of industry experience in SoC, AI accelerator, GPU, networking ASIC, or high-performance digital design.
• Proven experience performing RTL and gate-level power analysis and applying ASIC low-power design techniques.
• Strong understanding of computer architecture and SoC design trade-offs.
• Proficiency with scripting for automation and data analysis (Python, Perl, or similar).
• Strong analytical, debugging, and problem-solving skills.
• Ability to work independently in a fast-paced environment and communicate clearly across teams.
• Must be authorized to work in the United States and able to work from the Mountain View office Tuesdays–Thursdays.
• Familiarity with U.S. export-control constraints for controlled information is required.

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, or a related technical field.

Nice-to-have / Bonus

Additional skills that strengthen candidacy.

• RTL development experience (Verilog/SystemVerilog).
• Experience with clock distribution, multiple clock domains, clock gating, and power-aware RTL design.
• Experience with synthesis, static timing analysis, place-and-route, and implementation flows.
• Experience using power-analysis tools and developing power models, budgeting methodologies, and projection flows.
• Experience analyzing large power datasets and correlating pre-silicon estimates with silicon measurements.
• Experience with AI workload characterization and power-performance analysis.

About the Company

Company: MatX

Headquarters: Mountain View, California, USA

MatX specializes in creating faster chips for large language models (LLMs), focusing on innovative hardware and software solutions. The company fosters a collaborative and supportive work environment, welcoming candidates of all experience levels. Their approach prioritizes deep understanding and consideration of novel methods to drive efficiency and performance in their projects, particularly in silicon design and related engineering roles.