Senior SoC Power Analysis & Optimization Engineer

Job Title

Senior SoC Power Analysis & Optimization Engineer

Role Summary

Work on power estimation, analysis, modeling, and optimization for an AI accelerator SoC. Collaborate with architects, RTL designers, and physical-design teams to define power targets, improve power efficiency across compute, memory, interconnect, clock/reset and I/O subsystems, and support sign-off scenarios.

Experience Level

Senior — the role expects experienced engineers (posting specifies 8+ years of relevant industry experience).

Responsibilities

Key responsibilities include:

• Develop and maintain power estimation and energy-modeling methodologies for SoC and accelerator designs.
• Build and calibrate energy models for early architectural exploration and power-target definition.
• Perform RTL, gate-level, and post-layout power analysis across major SoC subsystems.
• Analyze AI workloads and usage scenarios to identify dynamic and static power reduction opportunities.
• Drive power-optimization efforts across compute, memory, interconnect, PCIe, HBM, clock/reset domains, and other subsystems.
• Collaborate with architects and RTL teams to implement power-aware microarchitecture and RTL improvements.
• Work with physical-design teams to evaluate implementation-related power trade-offs and correlate pre- and post-silicon estimates.
• Define representative workloads and sign-off scenarios to improve power-analysis coverage.
• Develop automation, scripts, dashboards, and heuristics to accelerate analysis and root-cause investigations.
• Present findings and recommendations to cross-functional teams and stakeholders.

Requirements

Must-have skills and constraints:

• 8+ years of industry experience in SoC, AI accelerator, GPU, networking ASIC, or high-performance digital design.
• Strong understanding of computer architecture and SoC design principles.
• Practical experience with ASIC low-power design techniques and power-aware RTL design.
• Experience performing RTL and gate-level power analysis and working with power-analysis flows.
• Proficiency with scripting for automation and data analysis (Python, Perl, or similar).
• Strong analytical, debugging, and data-analysis skills.
• Ability to work independently in a fast-paced environment and collaborate across teams; strong communication skills.
• Must be authorized to work in the United States and able to work from the Mountain View office Tuesday–Thursday.
• Role requires compliance with U.S. export-control restrictions; employment may be contingent on the ability to work without an export license.

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, or a related technical field.

About the Company

Company: MatX

Headquarters: Mountain View, California, USA

MatX specializes in creating faster chips for large language models (LLMs), focusing on innovative hardware and software solutions. The company fosters a collaborative and supportive work environment, welcoming candidates of all experience levels. Their approach prioritizes deep understanding and consideration of novel methods to drive efficiency and performance in their projects, particularly in silicon design and related engineering roles.