Senior SoC Physical Layout & Full-Chip Integration Engineer

Job Title

Senior SoC Physical Layout & Full-Chip Integration Engineer

Role Summary

Work on full-chip floorplanning, physical integration, and tapeout execution for advanced-node testchips and silicon lead vehicles within Intel Foundry's Design Technology Platform.

The role focuses on developing custom layout methodologies, physical verification closure, automation, and cross-functional coordination with PDK, EDA, and technology teams.

Experience Level

Senior - position expects experienced engineers. Minimum qualifications indicate candidates typically have 4+ years (Master's) or 1+ year (PhD) of relevant industry experience.

Responsibilities

Primary responsibilities include full-chip integration, layout methodology, verification, automation, and cross-team coordination.

• Lead full-chip floorplanning, physical integration, and tapeout activities for advanced-node silicon development vehicles.
• Develop and enhance custom layout methodologies and physical design flows for analog/mixed-signal blocks and full-chip integration.
• Drive physical verification closure for DRC, LVS, DFM, density, and antenna rules.
• Collaborate with Technology Development, PDK, and EDA teams to implement scalable and manufacturable solutions.
• Analyze advanced-node design rules and contribute to design enablement for FinFET and GAA process architectures.
• Develop automation scripts (Tcl, Python, SKILL) for layout creation, checking, and full-chip database manipulation.
• Coordinate cross-functional activities to ensure tape-in readiness, database integrity, and successful project execution.

Requirements

Must-have technical skills and demonstrated experience required for initial consideration. Preferred items listed separately.

• Custom/analog/mixed-signal layout design experience in advanced technology nodes (FEOL focus, transistor-level matching, parasitic-aware layout).
• Proven debugging and closure experience in physical verification: DRC, LVS, DFM using industry-standard engines (e.g., Calibre, ICV).
• Hands-on scripting for automation and database manipulation using Tcl, Python, or SKILL.
• Experience with full-chip database handling and integration workflows; familiarity with NDM-style flows for full-chip assembly.
• Track record of delivering tapeout schedules, coordinating IP matrices, and ensuring physical design QA and database integrity.

Nice-to-have:

• Top-level floorplanning, RDL/bump planning, or backside power delivery (PowerVia) implementation experience.
• Experience collaborating with PDK and Technology Development on rule definitions, test-structure vehicles, or DRC suppression strategies.
• Familiarity with Cadence Virtuoso custom layout environments and translating custom databases into full-chip flows.
• Previous foundry or silicon manufacturing experience.

Education Requirements

Master's degree in Electrical Engineering, Computer Engineering, or a related field with 4+ years of industry experience, OR PhD in the same fields with 1+ years of industry experience. Fields specified: Electrical Engineering, Computer Engineering, or related technical disciplines.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.