Senior SOC Physical Design Engineer

Job Title

Senior SOC Physical Design Engineer

Role Summary

Join the Cloud-Scale Machine Learning Acceleration team at Annapurna Labs to drive physical implementation, verification and tapeout of custom SoCs used in AWS machine learning servers (Inferentia, Trainium). The role focuses on full-chip floorplanning, physical verification, foundry interaction and integration for advanced process nodes.

Experience Level

Senior-level. The posting requires MS + 7 years or BS + 10 years of relevant experience; additionally expects 5+ years in physical verification for advanced technology nodes.

Responsibilities

Primary responsibilities include chip-level physical design, verification and mentoring.

• Drive full-chip floorplan, placement, integration, PV signoff and tapeout.
• Collaborate with front-end teams to address RTL and physical constraints early in the design cycle.
• Define, execute and optimize physical verification and integration methodologies using industry-standard EDA tools (e.g., Calibre, IC Validator).
• Perform DRC, LVS and PERC verification; debug and resolve physical verification issues with layout and design teams.
• Interface with foundries on rule deck updates, MT forms and waiver processes.
• Develop and maintain verification runsets, signoff flows and DFM/reliability checks (ESD, EM, IR drop).
• Mentor and provide technical guidance to junior engineers.

Requirements

Must-have technical skills and experience.

• Experience scripting in Python, Perl, Bash or PowerShell.
• 5+ years of physical verification experience for advanced technology nodes.
• Knowledge of backend physical design flows and tools (e.g., Fusion Compiler, Innovus).
• Expertise with industry-standard physical verification tools (Calibre, IC Validator, PVS).
• Strong understanding of semiconductor manufacturing processes and design rules; proven tape-out experience.
• Strong communication and collaboration skills.

Nice-to-have:

• Experience mentoring, leading, or managing junior engineers.
• Experience with integration and verification at advanced nodes (5nm or below).
• Knowledge of custom and digital design flows, DFM methodologies, and reliability verification.
• Experience with DDR, PCIe, fabrics and extraction/analysis of QOR metrics.

Los Angeles County applicants: pursuant to the LA County Fair Chance Ordinance, qualified applicants with arrest and conviction records will be considered.

Education Requirements

BS in Electrical Engineering, Computer Science or a related field with 10+ years of relevant experience, or MS in EE/CS or related field with 7+ years. The posting indicates these degree-and-experience combinations as the baseline; equivalent practical experience is implied as an alternative.

About the Company

Company: Amazon

Headquarters: Seattle, Washington, United States

Amazon is a global leader in e-commerce and cloud computing, committed to delivering fast, reliable services across diverse sectors. The company's innovative technologies include AWS, Kindle, and Echo, as well as developing low Earth orbit satellite networks for improved internet connectivity worldwide.