Senior SoC Performance Architect

Job Title

Senior SoC Performance Architect

Role Summary

Lead workload-driven performance analysis and modeling for server SoC products across hardware and software stacks. Work with architecture, design, software, and systems teams to identify bottlenecks, build performance projections, and recommend optimizations for CPU, memory, fabric, I/O, firmware, OS, compilers, and applications.

Experience Level

Senior — expected experience in CPU performance modeling and server-class system analysis. Typical background: multi-year industry experience (see Education Requirements for formal experience combinations).

Responsibilities

Analyze and improve end-to-end system performance for server workloads. Key activities include:

• Drive workload-based performance analysis and characterization for CPU- and system-intensive server workloads.
• Enable, run, and validate complex workloads on pre-silicon and post-silicon platforms and testbeds.
• Perform bottleneck analysis across cores, caches, memory hierarchy, on-chip fabric, memory controllers, and I/O subsystems.
• Build analytical and empirical models for workload behavior, scaling, and sensitivity to architectural and software parameters.
• Produce performance projections for internal products and competitive offerings.
• Identify cross-stack optimization opportunities and drive recommendations to architecture, design, compiler, OS, firmware, and application teams.
• Use profiling and PMU data, CPI decomposition, hotspot analysis, and microarchitectural stall analysis to root-cause performance issues.
• Define metrics, KPIs, and methodologies for workload analysis and performance tracking; present findings to technical and executive audiences.

Requirements

Must-have technical skills and experience (concise):

• Deep knowledge of CPU microarchitecture: pipelines, out-of-order execution, branch prediction, caches, prefetching, SMT, and performance bottlenecks.
• Experience with SoC-level architecture including on-chip interconnects/fabric, memory controllers, DRAM systems, coherency, and I/O subsystems.
• Strong understanding of OS and compiler interactions that affect performance (scheduling, memory management, synchronization, code generation).
• Hands-on experience using industry-standard performance analysis and profiling tools; ability to collect and interpret PMU and profiling datasets.
• Proven experience enabling and debugging complex server workloads on Linux-based environments.
• Analytical and scripting skills for processing large profiling datasets and building performance models.
• Track record of cross-functional collaboration and influencing HW/SW roadmaps through data-driven analysis.

Nice-to-have:

• Pre-silicon performance modeling, simulation, or trace-based analysis experience.
• Experience across server workloads: cloud, enterprise, data analytics, web, databases, virtualization, and AI infra.
• Familiarity with firmware/BIOS tuning, power/performance controls, and system configuration optimization.
• Experience presenting architecture recommendations to senior technical leadership.

Education Requirements

Posting references Bachelor's, Master's, and PhD degrees in Computer Engineering, Electrical Engineering, Computer Science, or related fields with corresponding experience combinations: Bachelor's +6 years, Master's +5 years, or PhD +4 years (alternative phrasing in Qualifications also notes PhD +5+ years for some preferred roles). Equivalent practical experience is implicitly acceptable per industry norms. Certifications were not specified.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.