Senior SOC Design For Test Engineer

Job Title

Senior SOC Design For Test Engineer

Role Summary

The Senior SOC Design For Test (DFT) Engineer will define, implement, verify, and support advanced DFT solutions for complex SoC products used in Automotive and Industrial applications. The role works within the AI and Chip Engineering (ACE) team and interfaces with design, verification, product engineering, and manufacturing teams to deliver scalable, cost-effective DFT architectures and production test solutions.

Experience Level

Senior-level. The posting does not specify an exact years-of-experience range.

Responsibilities

Key responsibilities include design, verification, integration, and support of DFT capabilities across IP and SoC levels.

• Define and implement DFT architectures at IP, subsystem, and SoC levels based on product requirements.
• Develop and integrate DFT features: scan, ATPG, Memory BIST, Logic BIST, JTAG/boundary scan, and related test structures.
• Develop and execute ATPG patterns to meet target fault coverage (Stuck-At, Transition Delay, memory/logic BIST).
• Perform DFT verification, simulations, and validation of implemented test solutions.
• Collaborate with design, verification, physical design, and product engineering teams to ensure testability requirements are met.
• Support silicon bring-up and post-silicon validation; analyze test failures, debug root causes, and drive yield/quality improvements.
• Work with manufacturing and ATE teams to enable efficient production test flows and evaluate test results.
• Document DFT architecture, implementation details, verification strategies, and test plans; provide technical leadership and mentorship.

Requirements

Must-have technical skills and experience for successful performance in this role.

• Proven experience in DFT design and verification for complex ASIC or SoC products.
• Solid understanding of DFT methodologies: scan design, ATPG, memory BIST, logic BIST, JTAG/boundary scan.
• Experience with industry DFT toolchains (examples: Synopsys TestMAX, Cadence Modus, Siemens Tessent).
• Good understanding of digital design fundamentals, ASIC/SoC development flows, and manufacturing test concepts.
• Experience with Verilog/SystemVerilog.
• Programming or scripting skills (TCL, Python, Perl, or similar) for tool integration and automation.
• Strong analytical, problem-solving, communication, and cross-functional collaboration skills.

Preferred (nice-to-have):

• Experience supporting silicon bring-up and post-silicon debug activities.
• Experience using AI tools to drive DFT conception and development.
• Familiarity with ATE test development and manufacturing test flows.
• Knowledge of advanced semiconductor process technologies.
• Experience on Automotive or Industrial semiconductor products.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Microelectronics, or a related field (as stated in the posting).

About the Company

Company: NXP Semiconductors

Headquarters: Nijmegen, Netherlands

NXP Semiconductors N.V. is a global semiconductor company that provides High Performance Mixed Signal and Standard Product solutions. With over 45,000 employees and operations in more than 35 countries, NXP is a leader in secure connectivity solutions for embedded applications, catering to automotive, industrial IoT, mobile, and communication infrastructure markets. The company is committed to innovation and sustainability, advancing a smarter, safer, and more sustainable world through technology.