Senior SoC Compute/Memory Subsystem Architect

Job Title

Senior SoC Compute/Memory Subsystem Architect

Role Summary

Senior architect responsible for end-to-end architecture of compute complexes, cache hierarchies, coherency models, and high-performance memory subsystems for next-generation IPU/DPU platforms.

Work within a cross-functional networking architecture group to optimize system-level performance, scalability, power efficiency, and programmability across compute, networking, storage, and accelerator domains.

Experience Level

Senior — minimum 7+ years of relevant industry experience in SoC, CPU, or memory subsystem architecture.

Responsibilities

Primary responsibilities include:

• Define compute complex architectures (core selection, cluster scaling, configuration tradeoffs) for IPU/DPU platforms.
• Specify compute subsystem roles (control plane, data-plane assists, offload execution, management services) and drive related architecture decisions balancing performance, power, and area.
• Design multi-level cache hierarchies and coherency models across CPU cores, accelerators, and IO subsystems.
• Architect system memory subsystems (DDR/LPDDR/HBM interfaces, memory controllers, scheduling policies, bandwidth provisioning and scaling).
• Define IO memory and virtualization architecture (SMMU/IOMMU) with multi-tenant isolation and memory model choices.
• Architect system-level integration across compute, network (packet pipelines), storage, and accelerators to optimize data movement and minimize latency and copies.
• Define power-efficiency and DVFS scaling strategies, including bandwidth throttling and per-subsystem scaling mechanisms.
• Lead multi-generation architecture roadmaps, ensuring scaling strategies and migration compatibility across product generations.
• Lead cross-functional alignment with networking, fabric/interconnect, firmware/OS/drivers, validation, and performance engineering teams.

Requirements

Key technical and professional requirements. Degree requirements are listed separately under Education Requirements.

• Must-have: 7+ years of hands-on experience in SoC/CPU/memory subsystem architecture, including CPU architecture and cache hierarchies.
• Must-have: Experience with memory subsystems (DDR, LPDDR, HBM), memory controllers, QoS, and bandwidth provisioning.
• Must-have: Expertise in coherent and non-coherent interconnect architectures and system-level performance and PPA tradeoff analysis.
• Must-have: Track record of driving architecture definition from concept through silicon delivery.
• Preferred: ARM and x86 compute and memory subsystem experience, including NUMA and large-scale platform architectures.
• Preferred: Experience with IPU/SmartNIC or accelerator-centric SoCs, cloud/hyperscale workloads, and virtualization-heavy platforms.
• Preferred: Familiarity with PCIe, CXL, memory semantics for high-performance IO, and multi-generation architectural ownership and mentoring.
• Behavioral: Strategic thinking, technical leadership, structured problem solving, strong cross-team collaboration, and ownership mindset.

Education Requirements

Minimum: Bachelor's degree in Electrical Engineering, Computer Engineering, or a STEM-related field. Preferred: Postgraduate degree in Electrical Engineering, Computer Engineering, or a related STEM field.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.