Senior SOC Clocks RTL Design Engineer

Job Title

Senior SOC Clocks RTL Design Engineer

Role Summary

Serve as the technical lead for SOC clocking RTL on next-generation networking chips. Implement clock generation, distribution, muxing/dividers, glitchless switching, clock gating, reset synchronization, and clock-domain crossing infrastructure, and drive designs from specification through tape-out and silicon bring-up.

This is an RTL design and technical leadership role working closely with Architecture, Design Verification, Physical Design, CAD, DFT, and Software teams.

Experience Level

Senior — 8+ years of relevant RTL/logic design experience, including multiple chips taken to tape-out.

Responsibilities

Lead implementation and delivery of SOC clocking RTL and coordinate across teams.

• Lead clocks development from specification through tape-out and bring-up.
• Translate clock/reset architecture into synthesizable Verilog/SystemVerilog RTL.
• Design clock generation, distribution, muxing, dividers, glitchless switching, gating, and reset synchronization.
• Set coding and quality standards, review RTL, and mentor other engineers.
• Collaborate with Physical Design on clock tree implementation, SDC/timing constraints, partitioning, and timing convergence.
• Partner with Design Verification on clocking test plans, gate-level debug, and coverage closure.
• Support software and firmware teams on clock programming, DVFS, and low-power/clock-shutdown flows.
• Represent clocking implementation in cross-functional design reviews.

Requirements

Must-have qualifications and skills.

• 8+ years of RTL/logic design experience with multiple chips taken to tape-out.
• Demonstrated technical leadership: leading a design area through implementation and tape-out and mentoring engineers.
• Expert hands-on RTL design in Verilog/SystemVerilog and strong understanding of how RTL choices affect synthesis, timing, area, and power.
• Deep knowledge of clocking and reset design: clock gating, muxing, dividers, glitchless switching, reset synchronization, and clock-domain crossing (CDC).
• Proficiency with design-quality tooling: lint, CDC/RDC, formal verification, synthesis, and static timing analysis (STA).
• Experience driving designs from architecture and micro-architecture through verification, physical implementation, and silicon bring-up.
• Strong communication and collaboration skills across micro-architecture, DV, backend, DFT, and software teams.

Nice-to-have:

• Hands-on SOC-level clocking or reset logic on a taped-out chip.
• PLL/clock generator integration and clock tree constraint development experience with backend teams.
• Experience with high-speed networking, interconnect, or fabric designs.
• Background in low-power techniques (clock gating, DVFS, power domains, UPF).
• Experience building automation for RTL integration or design-quality flows.

Education Requirements

B.Sc. or M.Sc. in Electrical Engineering or Computer Engineering.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.