Senior SoC Chiplet Architect

Job Title

Senior SoC Chiplet Architect

Role Summary

This role leads architecture strategy for chiplet-based SoC platforms targeted at next-generation data center workloads (compute, networking, memory/accelerators). The position drives chiplet partitioning, die-to-die interconnect architecture, system infrastructure (power/clock/boot/telemetry), and RAS/security across multi-die systems.

The role sits in the CEG Networking Architecture Group and requires cross-functional leadership with RTL, DV, firmware/software, packaging, and platform teams.

Experience Level

Senior — requires 7+ years of relevant experience in SoC/system architecture and multi-die/chiplet systems.

Responsibilities

Key responsibilities include defining architecture decisions and leading trade studies for scalable, modular chiplet-based SoCs.

• Define monolithic vs. chiplet decision framework and multi-generation roadmap considering reticle scaling, yield, modularity, and reuse.
• Lead architecture studies for multi-die scaling (2-/3-die and multi-chiplet topologies) covering partition boundaries, SKU scalability, and upgrade paths.
• Specify chiplet partitioning across compute, I/O/network, memory/accelerators, security/management to balance PPA, D2D bandwidth/latency, validation complexity, and product flexibility.
• Architect die-to-die (D2D) interconnects for bandwidth, latency, reliability, QoS, and flow control; align with industry standardization when applicable.
• Define system infrastructure across power delivery and management, clock/reset distribution, boot sequencing, and telemetry to ensure robust multi-die bring-up.
• Specify RAS, debug, and observability policies across chiplets for error reporting, containment, recovery, and post-silicon debug.
• Lead quantitative trade-off studies across performance, power, area, cost/yield, and schedule; coordinate with packaging and manufacturing stakeholders.
• Drive alignment across architecture, RTL, DV, FW/SW, packaging, and platform teams; produce executive-ready recommendations.

Requirements

Must-have qualifications and skills for initial consideration:

• 7+ years of experience in SoC/system architecture with end-to-end architecture definition from requirements to silicon execution.
• Practical experience with multi-die / chiplet partitioning and associated system implications (D2D, boot/reset coordination, cross-domain QoS, debug/observability).
• Proven ability to run architecture trade-off studies and present clear recommendations to senior technical and business stakeholders.
• Experience defining D2D interconnect requirements (bandwidth, latency, error handling, flow control) and QoS mechanisms.
• Experience specifying system-level power management, clock/reset strategies, and boot/firmware coordination across dies.
• Strong systems-level thinking, cross-functional influence, and executive communication skills.

Preferred:

• Familiarity with industry chiplet interoperability/standardization and participation in ecosystem discussions.
• Hands-on experience with system bring-up flows and architecture-driven debug/telemetry planning.
• Expertise in interconnects/fabrics, memory subsystem behavior, performance modeling, and PPA tradeoffs.
• Experience building or using cost/yield models for architectural decision-making.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or another STEM field of study is specified.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.