Senior SoC Chiplet Architect

Job Title

Senior SoC Chiplet Architect

Role Summary

Member of Intel's Central Engineering Group (Networking Architecture Group) responsible for defining architecture strategy for multi-die, chiplet-based SoC platforms targeting data center workloads. Leads chiplet partitioning, die-to-die interconnect architecture, system-level trade-off analysis, and cross-functional alignment.

The role drives modular, scalable SoC designs covering performance, power, area, cost/yield, boot/reset, telemetry, and RAS/security across multi-die systems.

Experience Level

Senior — requires 7+ years of industry experience in SoC/system architecture, including multi-die/chiplet partitioning and architecture trade studies.

Responsibilities

Primary responsibilities include:

• Define chiplet vs. monolithic decision framework and a multi-generation roadmap considering reticle limits, yield economics, modularity, and reuse.
• Lead functional partitioning and system topology for multi-die platforms (compute, I/O/network, memory, accelerators), balancing PPA, D2D bandwidth/latency, validation complexity, and product flexibility.
• Architect die-to-die interconnects, set link budgets and requirements for bandwidth, latency, error handling, flow control, and QoS mechanisms.
• Specify coordinated power delivery, clock/reset distribution, boot sequencing, and telemetry strategies across chiplets.
• Define cross-chiplet RAS, error reporting, containment, recovery policies, and debug/trace infrastructure for post-silicon and field diagnosability.
• Lead quantitative trade studies across performance, power, area, cost/yield, and schedule; partner with packaging and manufacturing stakeholders.
• Drive cross-functional alignment with architecture, RTL, DV, firmware/software, packaging, and platform teams and produce executive-ready architecture options.

Requirements

Minimum and preferred qualifications.

• Must-have: 7+ years experience in SoC/system architecture, including end-to-end architecture definition from requirements to silicon execution.
• Must-have: Practical experience with multi-die/chiplet partitioning and the associated system implications (die-to-die interfaces, boot/reset, cross-domain QoS, debug/observability).
• Must-have: Demonstrated ability to lead quantitative architecture trade-off studies and present clear recommendations to senior technical and business stakeholders.
• Nice-to-have: Familiarity with chiplet interoperability efforts and participation in ecosystem standardization discussions.
• Nice-to-have: Experience with system bring-up flows, interconnects/fabrics, memory subsystem behavior, performance modeling, and cost/yield modeling for architectural decision-making.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a STEM field as stated in the posting.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.